CN-122029541-A - Assessing power consumption

CN122029541ACN 122029541 ACN122029541 ACN 122029541ACN-122029541-A

Abstract

A computer-implemented method for evaluating power consumption of an electronic circuit design including at least one logic gate is disclosed. The method includes receiving one or more data files describing an electronic circuit design, describing waveform data describing signal activity of logic gates used in the electronic circuit design, and describing power consumption values of internal units of logic gates of the electronic circuit design (701). Waveform data is extracted from one or more data files describing signal activity at a main input of the electronic circuit design and outputs of registers and memory describing the electronic circuit design (702). Simulation of the logic gate is performed using the extracted waveform data to generate simulated waveform data describing a simulated logic conversion of an internal unit of the logic gate (703), and event-based evaluation of power consumption of the electronic circuit design is performed based on the extracted waveform data, the simulated waveform data, and the power consumption value (704).

Inventors

A. K. Deyi
VIJAY TAYAL

Assignees

西门子工业软件有限公司

Dates

Publication Date: 20260512
Application Date: 20231017

Claims (15)

1. A method for evaluating power consumption of an electronic circuit design, the electronic circuit design comprising at least one logic gate, the method being computer-implemented and comprising: Receiving one or more data files describing the electronic circuit design, waveform data describing signal activity of logic gates used in the electronic circuit design, and power consumption values of internal units of the logic gates describing the electronic circuit design; Extracting waveform data from the one or more data files describing signal activity at a main input of the electronic circuit design, and describing outputs of registers and memory of the electronic circuit design; Performing simulation of the logic gate using the extracted waveform data such that simulation waveform data describing a simulation logic conversion for the internal unit of the logic gate is generated, and An event-based evaluation of the power consumption of the electronic circuit design is performed based on the extracted waveform data, the analog waveform data, and the power consumption value.
2. The method of claim 1, wherein the one or more data files describe further waveform data describing further signal activity of the logic gate, and Wherein extracting the waveform data from the one or more data files includes examining the one or more data files to distinguish the waveform data describing the signal activity at the main input and the output of the register and memory of the electronic circuit design from the further waveform data describing the further signal activity of the logic gate.
3. The method of claim 1, further comprising: identifying analog waveform data used as input by a register or memory designed by the electronic circuit, and The identified analog waveform data is stored in a database in which it is associated with the respective register or memory that uses the identified analog waveform data as input.
4. The method of claim 1, further comprising: retrieving the power consumption values from the one or more data files, and The power consumption value is stored in a local memory.
5. The method of claim 1, further comprising performing the event-based assessment of power consumption during the performing of the simulation of the logic gate.
6. The method of claim 1, wherein said performing said simulation of said logic gate comprises reading said extracted waveform data with a time-based iterator.
7. The method of claim 1, further comprising identifying a connected logic gate and forming a connected component based on the connected logic gate, Wherein said performing said simulation of said logic gate comprises performing a simulation of said connected components in parallel, and Wherein said performing said event-based assessment comprises performing said event-based assessment of said connected component in parallel.
8. A computer system, comprising: at least one processor, and At least one memory including machine-readable instructions that, Wherein the at least one memory and the machine-readable instructions are configured to, with the at least one processor, cause the computer system to evaluate power consumption of an electronic circuit design, the electronic circuit design comprising at least one logic gate, the machine-readable instructions comprising: Receiving one or more data files describing the electronic circuit design, waveform data describing signal activity of logic gates used in the electronic circuit design, and power consumption values of internal units of the logic gates describing the electronic circuit design; Extracting waveform data from the one or more data files describing signal activity at a main input of the electronic circuit design and describing outputs of registers and memory of the electronic circuit design; Performing simulation of the logic gate using the extracted waveform data such that simulation waveform data describing a simulation logic conversion for the internal unit of the logic gate is generated, and An event-based evaluation of the power consumption of the electronic circuit design is performed based on the extracted waveform data, the analog waveform data, and the power consumption value.
9. The computer system of claim 8, wherein the one or more data files describe further waveform data describing further signal activity of the logic gate, and Wherein extracting the waveform data from the one or more data files includes examining the one or more files to distinguish the waveform data describing the signal activity at the main input of the electronic circuit design and the output of the register or the memory of the electronic circuit design from the further waveform data describing the further signal activity of the logic gate.
10. The computer system of claim 8, wherein the at least one memory and the machine-readable instructions are further configured to, with the at least one processor, cause the computer system to: identifying analog waveform data used as input by a register or memory designed by the electronic circuit, and The identified analog waveform data is stored in a database in which it is associated with the respective register or memory that uses the identified analog waveform data as input.
11. The computer system of claim 8, wherein the at least one memory and the machine-readable instructions are further configured to, with the at least one processor, cause the computer system to: retrieving the power consumption values from the one or more data files, and The power consumption value is stored in a local memory.
12. The computer system of claim 8, wherein the at least one memory and the machine-readable instructions are further configured to, with the at least one processor, cause the computer system to perform the event-based assessment of the power consumption during the performing of the simulation of the logic gate.
13. The computer system of claim 8, wherein said performing said simulation of said logic gate comprises reading said extracted waveform data with a time-based iterator.
14. A computer program comprising instructions which, when executed by a computer, cause the computer to perform the method of claims 1 to 7.
15. A data storage device having stored thereon a computer program according to claim 14.

Description

Assessing power consumption Technical Field The present disclosure relates to evaluating power consumption of electronic circuit designs. Background Digital electronic circuits include interconnected strings of logic cells that together perform a logic function on one or more input signals. Such circuits experience various power consumption sources such as switching power dissipation caused by charging and discharging of the capacitance at the cell output, leakage power dissipation caused by source-to-drain leakage, and internal power dissipation caused by, for example, transient shorts between the transistors of the cell and charging and discharging of the internal network. Power consumption is an important consideration in the design of electronic circuits, particularly Integrated Circuits (ICs). Which may typically include millions of transistors forming a logic cell. During the IC design process, the designer may use electronic design automation software to repeatedly evaluate the power consumption of the circuit at different stages of the design process, whereby the design may be modified if the power consumption does not meet the design specifications. Disclosure of Invention The power consumption of the integrated circuit may be evaluated based on switching activity data recorded by the designer in a switching activity file associated with the IC design, which may be generated by the designer using, for example, switching activity data provided by the semiconductor supplier. However, even with moderately complex ICs, reading all recorded signals from the switching activity file into the memory of the power consumption estimator may result in a significant amount of read time and memory resources. Accordingly, a first aspect of the present disclosure provides a computer-implemented method for evaluating power consumption, the electronic circuit design comprising at least one logic gate. The method includes receiving one or more data files describing an electronic circuit design, waveform data describing signal activity of logic gates used in the electronic circuit design, and power consumption values of internal units of the logic gates of the electronic circuit design. The method includes extracting waveform data from one or more data files describing signal activity at a main input of the electronic circuit design and outputs of registers and memories of the electronic circuit design, performing simulation of logic gates of the electronic circuit design using the extracted waveform data to generate simulated waveform data describing simulated logic conversions of internal cells of the logic gates, and performing event-based evaluation of power consumption of the electronic circuit design based on the extracted waveform data, the simulated waveform data, and the power consumption values. Thus, the main input of the circuit and the outputs of the registers and memories of the circuit are read from the signal activity file(s) to simulate the internal waveform. As a result, the read time associated with reading all signal activity waveforms from the data file(s) is reduced as compared to a scenario in which all waveform data is extracted from the signal activity file(s). Accordingly, overhead burden for performing the power evaluation method can be desirably reduced. In an implementation, the one or more data files describe further waveform data describing further signal activity of the logic gate, and extracting the waveform data from the file includes examining the file to distinguish the waveform data describing signal activity at the main input of the electronic circuit design and the output of the registers and memory of the electronic circuit design from the further waveform data describing further signal activity of the logic gate. In an implementation, the method further includes identifying analog waveform data used as input by registers and/or components of the electronic circuit design, and storing the waveform data in a database, wherein the waveform data is associated with registers or memory that use it as input. In an implementation, the method includes retrieving power consumption values from one or more data files and storing those power consumption values in a local memory. In an implementation, the method includes performing power consumption assessment during simulation. In an implementation, performing the simulation includes reading the extracted waveform data with a time-based iterator. In an implementation, the method includes identifying connected logic gates and forming connected components based on the connected logic gates. Performing the simulation of the logic gate includes performing the simulation of the connected components in parallel, and performing the event-based evaluation includes performing the event-based evaluation of the connected components in parallel. A second aspect of the present disclosure provides a computer system comprising at least one processor and a