CN-122029542-A - RFID tag rectifier with active bias ladder

CN122029542ACN 122029542 ACN122029542 ACN 122029542ACN-122029542-A

Abstract

The rectifier includes a main rectifier chain having sequentially coupled NMOS and PMOS rectifier elements, a first active bias ladder and a second active bias ladder. The first active bias ladder may be coupled to a first charge pump and include first and second bias tracking circuits. The first and second bias voltage tracking circuits bias the first and last NMOS rectifying elements of the main rectifying chain. The first active bias ladder may act as a voltage divider providing a bias to the intermediate NMOS rectifying element. Similarly, a second active bias ladder may be coupled to the second charge pump and include third and fourth voltage tracking circuits that bias the first and last PMOS rectifying elements. The second active bias ladder may also act as a voltage divider and provide bias to the intermediate PMOS rectifying element.

Inventors

DAI PANPAN
Fabrizio Matos
Laurent Kussel
John D. Heidi

Assignees

英频杰公司

Dates

Publication Date: 20260512
Application Date: 20241011
Priority Date: 20231013

Claims (10)

1. A rectifier for a Radio Frequency Identification (RFID) Integrated Circuit (IC), the rectifier comprising: a main rectifying chain comprising three or more rectifying stages, wherein each rectifying stage comprises a pair of sequentially coupled NMOS and PMOS rectifying elements; a first active bias ladder configured to bias the NMOS rectifying elements in the main rectifying chain; a first bias generator coupled to the first active bias ladder and the main rectifying chain, wherein the first bias generator is configured to provide a first bias to the first active bias ladder and comprises: A first charge pump coupled to a first point of the main rectifying chain, and A first bias voltage tracking circuit coupled to the first charge pump, a first point of the first active bias ladder, and a first NMOS rectifying element in the main rectifying chain, and A second bias generator coupled to the first active bias ladder and the main rectifying chain, wherein the second bias generator is configured to provide a second bias to the first active bias ladder and comprises: a second bias voltage tracking circuit is coupled to a second point of the first active bias ladder and to a second NMOS rectifying element in the main rectifying chain.
2. The rectifier of claim 1 further comprising: a second active bias ladder configured to bias the PMOS rectifying elements in the main rectifying chain; a third bias generator coupled to the second active bias ladder and the main rectifying chain, wherein the third bias generator is configured to provide a third bias to the second active bias ladder and comprises: A third bias voltage tracking circuit coupled to the first point of the second active bias ladder and the first PMOS rectifying element in the main rectifying chain, and A fourth bias generator coupled to the second active bias ladder and the main rectifying chain, wherein the fourth bias generator is configured to provide a fourth bias to the second active bias ladder and comprises: a second charge pump coupled to a second point of the main rectifying chain, and A fourth bias voltage tracking circuit coupled to the second charge pump, a second point of the second active bias ladder, and a second PMOS rectifying element in the main rectifying chain.
3. The rectifier of claim 2 wherein: each of the first bias voltage tracking circuit and the second bias voltage tracking circuit includes diode-connected NMOS transistors, and Each of the third bias voltage tracking circuits and the fourth bias voltage tracking circuits includes a diode-connected PMOS transistor.
4. The rectifier of claim 1 further comprising a first resistive element and a second resistive element, wherein: The first bias voltage tracking circuit is coupled to the first NMOS rectifying element in the main rectifying chain at: the drain electrode of the first NMOS rectifying element, and A gate of the first NMOS rectifying element passing through the first resistive element, and The second bias voltage tracking circuit is coupled to the second NMOS rectifying element in the main rectifying chain at: the drain electrode of the second NMOS rectifying element, and The gate of the second NMOS rectifying element passes through the second resistive element.
5. The rectifier of claim 2 further comprising a third resistive element and a fourth resistive element, wherein: the third bias voltage tracking circuit is coupled to the first PMOS rectifying element of the main rectifying chain at: the drain electrode of the first PMOS rectifying element, and A gate of the first PMOS rectifying element passing through the third resistive element, and The fourth bias voltage tracking circuit is coupled to the second PMOS rectifying element of the main rectifying chain at: The drain electrode of the second PMOS rectifying element, and The gate of the second PMOS rectifying element or the second charge pump passes through the fourth resistive element.
6. The rectifier of claim 1 wherein each transistor of the first active ladder and the second active ladder coupled to the rectifying element of the main rectifying chain is coupled to one of two opposite phases of a radio frequency signal.
7. The rectifier of claim 1 wherein at least one of the first charge pump and the first bias voltage tracking circuit is configurable to adjust the first bias based on an output voltage generated by the rectifier.
8. The rectifier of claim 7 wherein: The first charge pump is configurable to adjust the first bias by limiting a number of operational stages within the first charge pump; the first bias voltage tracking circuit includes a plurality of connectable transistor segments, and The first bias tracking circuit is configurable to adjust the first bias by connecting or disconnecting at least one of the connectable transistor sections.
9. The rectifier of claim 1 wherein only some, but not all, of the rectifying stages of the main rectifying chain are directly coupled to any of the first, second, third, or fourth bias generators.
10. A Radio Frequency Identification (RFID) Integrated Circuit (IC), comprising: antenna port, and A rectifier coupled to the antenna port, the rectifier comprising: a main rectifying chain comprising three or more rectifying stages, wherein each rectifying stage comprises a pair of sequentially coupled NMOS and PMOS rectifying elements; a first active bias ladder configured to bias the NMOS rectifying elements in the main rectifying chain; a first bias generator coupled to the first active bias ladder and the main rectifying chain, wherein the first bias generator is configured to provide a first bias to the first active bias ladder and comprises: A first charge pump coupled to a first point of the main rectifying chain, and A first bias voltage tracking circuit coupled to the first charge pump, a first point of the first active bias ladder, and a first NMOS rectifying element in the main rectifying chain, and A second bias generator coupled to the first active bias ladder and the main rectifying chain, wherein the second bias generator is configured to provide a second bias to the first active bias ladder and comprises: a second bias voltage tracking circuit is coupled to a second point of the first active bias ladder and to a second NMOS rectifying element in the main rectifying chain.

Description

RFID tag rectifier with active bias ladder Cross reference to related applications The present application claims priority from U.S. provisional patent application Ser. No. 63/590,040 filed on 10/13 of 2023. The disclosure of this provisional application is incorporated herein by reference in its entirety. Background Radio-Frequency Identification (RFID) systems typically include an RFID reader (also known as an RFID reader or RFID interrogator), and an RFID tag. RFID systems can be used in a variety of ways to locate and identify items to which a tag is attached. RFID systems are useful in the product-related and service-related industries for tracking items being handled, checked-in, or carried. In these cases, RFID tags are typically attached to individual items or to their packages. In principle, RFID technology involves the use of an RFID reader to inventory one or more RFID tags, where inventory involves separating (singulate) the tags individually and receiving identifiers from the individually separated tags. "separate (singulated)" is defined as the reader selecting a tag from a plurality of tags that may be present for a reader-tag conversation. An "identifier" is defined as a number that identifies the tag or the item to which the tag is attached, such as a tag identifier (TAG IDENTIFIER, TID), an electronic product code (electronic product code, EPC), and so forth. A reader transmitting Radio Frequency (RF) waves performs interrogation. The RF wave is typically an electromagnetic wave, at least in the far field. The RF wave may also be primarily electrical or magnetic in the near field or transition near field. The RF wave may encode one or more commands that instruct the tag to perform one or more actions. In a typical RFID system, an RFID reader transmits a modulated RF inventory signal (command), receives a tag reply, and transmits an RF acknowledgement signal in response to the tag reply. A tag that senses interrogating RF waves may respond by sending back another RF wave. The tag either originally generated the transmitted back RF wave or reflected a portion of the interrogating RF wave back through a process known as back scattering. Backscattering can be done in a number of ways. The reflected RF wave may encode data (such as a number) stored at the tag. The reader demodulates and decodes the response, thereby identifying, counting, or otherwise interacting with the associated item. The decoded data may represent a sequence number, price, date, time, destination, encrypted information electronic signature, other attribute(s), any combination of attributes, and so forth. Accordingly, when the reader receives the tag data, it can acquire the article information on which the tag is mounted and/or the tag itself information. RFID tags typically include an antenna section, a wireless section, a power management section, and often include logic, memory, or both. In some RFID tags, the power management section includes an energy storage device, such as a battery. RFID tags having energy storage devices are known as battery-assisted, semi-active or active tags. Other RFID tags may be powered solely by the RF signals they receive. These RFID tags do not include an energy storage device and are referred to as passive tags. Of course, even passive tags typically contain temporary energy as well as data/flag bit storage elements such as capacitors or inductors, etc. Disclosure of Invention This summary is provided to introduce a selection of concepts in a simplified form that are further described below in the detailed description. This summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter. Examples are directed to a rectifier for a Radio Frequency Identification (RFID) Integrated Circuit (IC). The rectifier includes a main rectifying chain including three or more rectifying stages, wherein each rectifying stage includes a pair of sequentially coupled n-channel metal oxide semiconductor (n-CHANNEL METAL oxide semiconductor, NMOS) and p-channel metal oxide semiconductor (p-CHANNEL METAL oxide semiconductor, PMOS) rectifying elements. The rectifier may also include a first active bias ladder configured to bias NMOS rectifying elements in the main rectifying chain. A first bias generator may be coupled to the first active bias ladder and the main rectifying chain. The first bias generator is configured to provide a first bias to the first active bias ladder. The first bias generator may include a first charge pump coupled to a first point of the main rectifying chain and a first bias voltage tracking circuit coupled to the first point of the first active bias ladder and a first NMOS rectifying element in the main rectifying chain. The rectifier may also include a second bias generator coupled to the first active bias ladder and the main rectifier chain. The secon