CN-122029590-A - Clock selection circuit, display device having the same, and driving method thereof

Abstract

A clock selection circuit according to an embodiment of the present invention includes a control circuit for outputting a first control signal and a second control signal when at least one of a previous stage scan signal or a next stage scan signal is input, and a selection circuit for receiving a clock signal and outputting the clock signal when the first control signal and the second control signal are input.

Inventors

• Jin Jinggao
• LI QICHANG
• HUANG SHENGYUN

Assignees

• 三星显示有限公司

Dates

Publication Date

20260512

Application Date

20240724

Priority Date

20231011

Claims (20)

1. 1. A clock selection circuit, comprising: A control circuit for outputting a first control signal and a second control signal when at least one of the previous stage scan signal or the next stage scan signal is inputted, and And a selection circuit for receiving a clock signal and outputting the clock signal when the first control signal and the second control signal are input.
2. 2. The clock selection circuit of claim 1, wherein the control circuit comprises: A first logic gate for receiving the previous stage scan signal via a first input terminal, receiving the next stage scan signal via a second input terminal, and outputting the first control signal via a first output terminal, and And a second logic gate for receiving the first control signal and outputting the second control signal from a second output terminal by inverting the first control signal.
3. 3. The clock selection circuit according to claim 2, wherein the previous stage scan signal and the next stage scan signal are set to a high level voltage, The first logic gate outputs the first control signal of a low level by performing a nor operation on the previous stage scan signal and the next stage scan signal.
4. 4. The clock selection circuit of claim 2, wherein the first logic gate comprises: A first transistor and a second transistor connected in series between the first power supply and the first node, and A third transistor and a fourth transistor connected in parallel with each other between the first node and a second power supply having a voltage lower than that of the first power supply, Wherein the first transistor and the second transistor are P-type transistors, and the third transistor and the fourth transistor are N-type transistors.
5. 5. The clock selection circuit of claim 4, wherein a gate electrode of the first transistor and a gate electrode of the third transistor are connected to the first input terminal, and A gate electrode of the second transistor and a gate electrode of the fourth transistor are connected to the second input terminal.
6. 6. The clock selection circuit of claim 5, wherein the first logic gate further comprises a third input that receives a current stage scan signal.
7. 7. The clock selection circuit of claim 6, wherein the first logic gate further comprises: a fifth transistor connected in series with the first transistor and the second transistor between the first power supply and the first node, and A sixth transistor connected in parallel with the third transistor and the fourth transistor between the first node and the second power supply, and The fifth transistor is a P-type transistor and the sixth transistor is an N-type transistor.
8. 8. The clock selection circuit of claim 7, wherein a gate electrode of the fifth transistor and a gate electrode of the sixth transistor are connected to the third input terminal.
9. 9. The clock selection circuit of claim 2, wherein the second logic gate is an inverter that outputs the second control signal by inverting the first control signal.
10. 10. The clock selection circuit of claim 9, wherein the second logic gate comprises a first transistor of a P-type and a second transistor of an N-type connected in series with each other between a first power supply and a second power supply, the second power supply having a voltage lower than a voltage of the first power supply, A gate electrode of the first transistor of the P-type and a gate electrode of the second transistor of the N-type are connected to the first output terminal, and a common node between the first transistor of the P-type and the second transistor of the N-type is connected to the second output terminal.
11. 11. The clock selection circuit of claim 1, wherein the selection circuit comprises: A first transmission gate connected between a first clock input terminal and a first clock output terminal and turned on when the first control signal and the second control signal are input, the first clock signal being input through the first clock input terminal, and And a second transmission gate connected between a second clock input terminal and a second clock output terminal, and turned on when the first control signal and the second control signal are input, the second clock signal being input through the second clock input terminal.
12. 12. The clock selection circuit of claim 11, wherein the first transmission gate comprises a first control transistor of a P-type and a second control transistor of an N-type connected in parallel with each other between the first clock input terminal and the first clock output terminal, The first control transistor of the P-type is turned on when the first control signal is input, and the second control transistor of the N-type is turned on when the second control signal is input.
13. 13. The clock selection circuit of claim 11, wherein the second transmission gate comprises a first control transistor of P-type and a second control transistor of N-type connected in parallel with each other between the second clock input terminal and the second clock output terminal, The first control transistor of the P-type is turned on when the first control signal is input, and the second control transistor of the N-type is turned on when the second control signal is input.
14. 14. A display device, comprising: a plurality of pixels arranged to be connected to a plurality of scan lines and a plurality of data lines; A scan driver for supplying scan signals to the plurality of scan lines; A clock controller for sequentially outputting a first control signal and a second control signal in units of horizontal lines in response to the scan signals sequentially input in units of horizontal lines, and And a clock selector for receiving a clock signal required to drive the scan driver and supplying the clock signal to the scan driver in units of the horizontal lines in response to the first control signal and the second control signal.
15. 15. The display device of claim 14, wherein the scan driver includes a stage circuit on each of the horizontal lines, The clock controller includes a control circuit on each horizontal line, and The clock selector includes a selection circuit located on each of the horizontal lines.
16. 16. The display device according to claim 15, wherein the stage circuit located on the first horizontal line receives a scan start signal, and A control circuit located on the first horizontal line receives a clock start signal overlapping the scan start signal.
17. 17. The display device according to claim 15, wherein the control circuit located on the last horizontal line receives an end signal overlapped with the scan signal corresponding to the last horizontal line during a partial period.
18. 18. The display device according to claim 15, wherein an ith control circuit located on an ith (i is a natural number) horizontal line outputs the first control signal and the second control signal in response to a previous scan signal of a previous horizontal line and a next scan signal of a next horizontal line.
19. 19. The display device according to claim 18, wherein the i-th control circuit includes: A first logic gate for generating the first control signal by performing a NOR operation on the previous scan signal and the next scan signal, and And a second logic gate for generating the second control signal by inverting the first control signal.
20. 20. The display device according to claim 15, wherein an i (i is a natural number) control circuit located on an i-th horizontal line outputs the first control signal and the second control signal in response to a previous scan signal of a previous horizontal line, a current scan signal of a current horizontal line, and a next scan signal of a next horizontal line.

Description

Clock selection circuit, display device having the same, and driving method thereof Technical Field The present invention relates to a clock selection circuit, a display device including the same, and a method of driving the display device. Background With the development of information society, the demand for display devices for displaying images is increasing in various forms. For example, display devices are being applied to various electronic devices such as smart phones, digital cameras, notebook computers, navigation devices, and smart televisions. The display device displays an image using pixels. The display device may include a plurality of scan drivers driving the pixels. Disclosure of Invention Technical problem An object of the present invention is to provide a clock selection circuit capable of minimizing power consumption, a display device including the clock selection circuit, and a method of driving the display device. Technical proposal According to an embodiment of the present invention, a clock selection circuit includes a control circuit for outputting a first control signal and a second control signal when at least one of a previous stage scan signal or a next stage scan signal is input, and a selection circuit for receiving a clock signal and outputting the clock signal when the first control signal and the second control signal are input. According to one embodiment, the control circuit includes a first logic gate for receiving a previous stage scan signal through a first input terminal, receiving a next stage scan signal through a second input terminal, and outputting a first control signal through a first output terminal, and a second logic gate for receiving the first control signal and outputting a second control signal through a second output terminal by inverting the first control signal. According to an embodiment, the previous stage scan signal and the next stage scan signal are set to high level voltages, and the first logic gate outputs the first control signal of low level by performing a nor operation on the previous stage scan signal and the next stage scan signal. According to an embodiment, the first logic gate includes a first transistor and a second transistor connected in series with each other between the first power supply and the first node, and a third transistor and a fourth transistor connected in parallel with each other between the first node and the second power supply, the second power supply having a voltage lower than that of the first power supply, the first transistor and the second transistor being P-type transistors, the third transistor and the fourth transistor being N-type transistors. According to an embodiment, the gate electrode of the first transistor and the gate electrode of the third transistor are connected to the first input terminal, and the gate electrode of the second transistor and the gate electrode of the fourth transistor are connected to the second input terminal. According to one embodiment, the first logic gate further comprises a third input terminal for receiving a current stage scan signal. According to an embodiment, the first logic gate further includes a fifth transistor connected in series with the first transistor and the second transistor between the first power supply and the first node, and a sixth transistor connected in parallel with the third transistor and the fourth transistor between the first node and the second power supply, the fifth transistor being a P-type transistor, the sixth transistor being an N-type transistor. According to an embodiment, a gate electrode of the fifth transistor and a gate electrode of the sixth transistor are connected to the third input terminal. According to one embodiment, the second logic gate is an inverter outputting the second control signal by inverting the first control signal. According to an embodiment, the second logic gate includes a P-type first transistor and an N-type second transistor connected in series with each other between a first power source and a second power source, the second power source having a voltage lower than that of the first power source, a gate electrode of the P-type first transistor and a gate electrode of the N-type second transistor being connected to the first output terminal, and a common node between the P-type first transistor and the N-type second transistor being connected to the second output terminal. According to one embodiment, the selection circuit includes a first transmission gate connected between the first clock input terminal and the first clock output terminal and turned on when the first control signal and the second control signal are input, the first clock signal being input through the first clock input terminal, and a second transmission gate connected between the second clock input terminal and the second clock output terminal and turned on when the first control signal and the second control signal are input, the second