CN-122029594-A - Display with silicon gate driver and semiconductor oxide pixels

Abstract

The display may include an array of pixels that receive control signals from a gate driver chain. The pixels may be formed using semiconductor oxide transistors and the gate driver may be formed using silicon transistors. Each gate driver may include a shift register sub-circuit and an output buffer sub-circuit. The shift register subcircuit may include a first set of transistors controlled at least in part by one or more shift register clock signals. The output buffer sub-circuit may include a second set of transistors controlled at least in part by one or more output buffer clock signals. The output buffer clock signal may be switched independently of the shift register clock signal. Operating in this manner, the shift register clock signal may have a pulse width optimized for stability, while the output buffer clock signal may have a pulse width optimized for speed.

Inventors

• ONO SHINYA
• LIN JINGWEI
• CHEN ZHENMING
• H. Adris

Assignees

• 苹果公司

Dates

Publication Date

20260512

Application Date

20240924

Priority Date

20240109

Claims (20)

1. 1. A display gate driver circuit, the display gate driver circuit comprising: A shift register sub-circuit configured to receive a shift register clock signal, receive a carry input signal, and generate a carry output signal, and An output buffer sub-circuit configured to receive an output buffer clock signal and to generate a corresponding gate output signal, the output buffer sub-circuit comprising: A first transistor having a first source-drain terminal configured to receive the output buffer clock signal, a second source-drain terminal at which the gate output signal is generated, and a gate terminal; a second transistor having a first source-drain terminal coupled to a second source-drain terminal of the first transistor, a second source-drain terminal coupled to a power line, and a gate terminal, and A third transistor having a gate terminal coupled to the gate terminal of the first transistor, a first source-drain terminal coupled to the gate terminal of the second transistor, and a second source-drain terminal coupled to a given node within the shift register subcircuit.
2. 2. The display gate driver circuit of claim 1, wherein the output buffer sub-circuit further comprises: a fourth transistor having a gate terminal coupled to the power supply line, a first source-drain terminal coupled to a second source-drain terminal of the third transistor, and a second source-drain terminal coupled to the given node within the shift register sub-circuit.
3. 3. The display gate driver circuit of claim 2, wherein the output buffer sub-circuit further comprises: A first capacitor coupled between a gate terminal and a second source-drain terminal of the first transistor; A second capacitor having a first terminal coupled to the gate terminal of the second transistor and having a second terminal, and A third capacitor having a first terminal coupled to the second terminal of the second capacitor and having a second terminal coupled to the power line.
4. 4. The display gate driver circuit of claim 3, wherein the output buffer sub-circuit further comprises: a fifth transistor having a first source-drain terminal coupled to the second terminal of the second capacitor, a second source-drain terminal configured to receive one of the shift register clock signals, and a gate terminal, and A sixth transistor having a first source-drain terminal coupled to the gate terminal of the fifth transistor, a second source-drain terminal coupled to another display gate driver circuit, and a gate terminal coupled to the power supply line.
5. 5. The display gate driver circuit of claim 4, wherein the output buffer sub-circuit further comprises: a seventh transistor having a first source-drain terminal coupled to the gate terminal of the first transistor, a gate terminal coupled to the power line, and a second source-drain terminal, and A plurality of transistors connected in series between the power supply line and an additional power supply line, wherein a second source-drain terminal of the seventh transistor is coupled to a node disposed along the plurality of serially connected transistors.
6. 6. The display gate driver circuit of claim 4, wherein the output buffer sub-circuit further comprises: a seventh transistor having a first source-drain terminal coupled to the second terminal of the second capacitor, a second source-drain terminal coupled to the power line, and a gate terminal configured to receive a reset signal pulsed during a vertical blanking period.
7. 7. A display gate driver circuit, the display gate driver circuit comprising: A shift register sub-circuit configured to receive a shift register clock signal, receive a carry input signal, and generate a carry output signal, and An output buffer sub-circuit configured to receive an output buffer clock signal and to generate a corresponding gate output signal, the output buffer sub-circuit comprising: A first silicon transistor having a first source-drain terminal configured to receive the output buffer clock signal, a second source-drain terminal at which the gate output signal is generated, and a gate terminal; a capacitor coupled across the gate terminal and the second source-drain terminal of the first silicon transistor, and A second semiconductor oxide transistor having a first source-drain terminal coupled to the second source-drain terminal of the first silicon transistor, a second source-drain terminal coupled to a power supply line, and a gate terminal.
8. 8. The display gate driver circuit of claim 7, wherein a gate terminal of the second semiconductor oxide transistor is coupled to a given node within the shift register sub-circuit.
9. 9. The display gate driver circuit of claim 7, wherein the output buffer sub-circuit further comprises: A third silicon transistor having a first source-drain terminal coupled to the gate terminal of the first silicon transistor, a gate terminal coupled to the power line, and a second source-drain terminal, and A plurality of silicon transistors connected in series between the power supply line and an additional power supply line, wherein a second source-drain terminal of the third silicon transistor is coupled to a node disposed along the plurality of series-connected silicon transistors.
10. 10. The display gate driver circuit of claim 9, wherein the output buffer sub-circuit further comprises: A fourth silicon transistor having a first source-drain terminal coupled to the gate terminal of the second semiconductor oxide transistor, a second source-drain terminal coupled to the additional power supply line, and a gate terminal configured to receive a reset signal pulsed during a vertical blanking period.
11. 11. The display gate driver circuit of claim 9, wherein a gate terminal of the second semiconductor oxide transistor is coupled to the node disposed along the plurality of series-connected silicon transistors.
12. 12. The display gate driver circuit of claim 7, wherein a gate terminal of the second semiconductor oxide transistor is coupled to a gate terminal of the first silicon transistor.
13. 13. The display gate driver circuit of claim 12, wherein the output buffer sub-circuit further comprises: A third silicon transistor having a first source-drain terminal coupled to the gate terminal of the first silicon transistor, a gate terminal coupled to the power line, and a second source-drain terminal; a fourth semiconductor oxide transistor having a first source-drain terminal coupled to the power supply line, a second source-drain terminal coupled to a second source-drain terminal of the third silicon transistor, and a gate terminal, and A fifth silicon transistor having a first source-drain terminal coupled to the second source-drain terminal of the fourth semiconductor oxide transistor, a second source-drain terminal coupled to an additional power supply line, and a gate terminal shorted to the gate terminal of the fourth semiconductor oxide transistor.
14. 14. The display gate driver circuit of claim 13, wherein the output buffer sub-circuit further comprises: a sixth silicon transistor having a first source-drain terminal coupled to the gate terminal of the second semiconductor oxide transistor, a second source-drain terminal coupled to the additional power supply line, and a gate terminal configured to receive a reset signal pulsed during a vertical blanking period.
15. 15. The display gate driver circuit of claim 13, wherein the output buffer sub-circuit further comprises: a sixth silicon transistor having a first source-drain terminal coupled to the fourth semiconductor oxide transistor, a second source-drain terminal coupled to the fifth silicon transistor, and a gate terminal coupled to one of the shift register clock signals.
16. 16. A display gate driver circuit, the display gate driver circuit comprising: A shift register sub-circuit configured to receive a shift register clock signal, receive a carry input signal, and generate a carry output signal, wherein the shift register sub-circuit includes only silicon transistors and a plurality of capacitors, and An output buffer sub-circuit configured to receive an output buffer clock signal and to generate a corresponding gate output signal, the output buffer sub-circuit comprising: A first semiconductor oxide transistor having a first source-drain terminal configured to receive the output buffer clock signal, a second source-drain terminal at which the gate output signal is generated, and a gate terminal, and A second semiconductor oxide transistor having a first source-drain terminal coupled to the first semiconductor oxide transistor, a second source-drain terminal coupled to a power supply line, and a gate terminal coupled to a given node within the shift register sub-circuit.
17. 17. The display gate driver circuit of claim 16, wherein the output buffer sub-circuit further comprises: A capacitor coupled across the gate terminal and the second source-drain terminal of the first semiconductor oxide transistor.
18. 18. The display gate driver circuit of claim 17, wherein the output buffer sub-circuit further comprises: A third semiconductor oxide transistor having a first source-drain terminal coupled to the gate terminal of the first semiconductor oxide transistor, a gate terminal coupled to the power supply line, and a second source-drain terminal coupled to an additional node within the shift register sub-circuit.
19. 19. The display gate driver circuit of claim 18, wherein the output buffer sub-circuit further comprises: a fourth transistor having a first source-drain terminal coupled to the gate terminal of the second semiconductor oxide transistor, a second source-drain terminal coupled to an additional power line different from the power line, and a gate terminal configured to receive a reset signal.
20. 20. The display gate driver circuit of claim 19, wherein the fourth transistor comprises a silicon transistor.

Description

Display with silicon gate driver and semiconductor oxide pixels The present application claims the benefit of U.S. patent application Ser. No. 18/407,578, filed on 1 month 9 of 2024, and U.S. provisional patent application Ser. No. 63/592,879, filed on 24 of 10 month 2023, each of which is incorporated herein by reference in its entirety. Background The present disclosure relates generally to electronic devices having displays, and more particularly to display driver circuits for displays such as Organic Light Emitting Diode (OLED) displays. Electronic devices typically include a display. For example, cellular telephones, tablet computers, wrist watches, and portable computers typically include a display for presenting image content to a user. An OLED display has an array of display pixels based on light emitting diodes. In this type of display, gate driver circuitry is used to provide control signals to individual rows in the display pixel array. Designing the gate driver circuit can be challenging. Disclosure of Invention An electronic device may include a display having an array of display pixels. The display pixels may be organic light emitting diode display pixels. Each display pixel may include an Organic Light Emitting Diode (OLED) that emits light, one or more storage capacitors, and a semiconductor-only oxide transistor, such as an n-type semiconductor oxide transistor. A chain of gate driver circuits may be used to drive the display pixel array. The gate driver circuit may be implemented using only silicon transistors (such as p-type low temperature polysilicon transistors) or using a combination of silicon transistors and semiconductor oxide transitions. Implementing all pixel transistors as semiconductor oxide transistors may enable low refresh rate operation, such as display refresh rates below 10Hz or as low as 1Hz or less, while implementing all or most gate driver transistors as silicon transistors may help to improve gate driver robustness. One aspect of the present disclosure provides a display gate driver circuit including a shift register sub-circuit configured to receive a shift register clock signal, receive a carry input signal, and generate a carry output signal, and an output buffer sub-circuit configured to receive an output buffer clock signal and generate a corresponding gate output signal. The output buffer sub-circuit may include a first transistor having a first source-drain terminal configured to receive an output buffer clock signal, a second source-drain terminal at which a gate output signal is generated, and a gate terminal, a second transistor having a first source-drain terminal coupled to the second source-drain terminal of the first transistor, a second source-drain terminal coupled to a power line, and a gate terminal, and a third transistor having a gate terminal coupled to the gate terminal of the first transistor, a first source-drain terminal coupled to the gate terminal of the second transistor, and a second source-drain terminal coupled to a given node within the shift register sub-circuit. One aspect of the present disclosure provides a gate driver circuit including a shift register sub-circuit configured to receive a shift register clock signal, receive a carry input signal, and generate a carry output signal, and an output buffer sub-circuit configured to receive an output buffer clock signal and generate a corresponding gate output signal. The output buffer sub-circuit may include a first silicon transistor having a first source-drain terminal configured to receive an output buffer clock signal, a second source-drain terminal at which a gate output signal is generated, and a gate terminal, a capacitor coupled across the gate terminal and the second source-drain terminal of the first silicon transistor, and a second semiconductor oxide transistor having a first source-drain terminal coupled to the second source-drain terminal of the first silicon transistor, a second source-drain terminal coupled to the power line, and a gate terminal. One aspect of the present disclosure provides a gate driver circuit including a shift register sub-circuit configured to receive a shift register clock signal, receive a carry input signal, and generate a carry output signal, wherein the shift register sub-circuit includes only silicon transistors and a plurality of capacitors, and an output buffer sub-circuit configured to receive an output buffer clock signal and generate a corresponding gate output signal. The output buffer sub-circuit may include a first semiconductor oxide transistor having a first source-drain terminal configured to receive the output buffer clock signal, a second source-drain terminal at which the gate output signal is generated, and a gate terminal, and a second semiconductor oxide transistor having a first source-drain terminal coupled to the first semiconductor oxide transistor, a second source-drain terminal coupled to the power supply line, and a g