CN-122029603-A - Method and apparatus for dual edge memory write operation

Abstract

An apparatus for a dual edge memory write operation is provided. The apparatus may include a write enable circuit to receive a write enable signal for writing data to a memory cell, and a write drive circuit to receive a data signal and a complementary data signal and output a bus signal and a complementary bus signal to the memory cell. The write driver circuit may be coupled to the write enable circuit. The write enable circuit may initiate a write operation to write data to the memory cell based on a falling edge of the write enable signal.

Inventors

• J.Jin

Assignees

• 美高森美SoC公司

Dates

Publication Date

20260512

Application Date

20241014

Priority Date

20241012

Claims (20)

1. 1. An apparatus, the apparatus comprising: A write enable circuit for receiving a write enable signal for writing data to the memory cell, and A write drive circuit for receiving a data signal and a complementary data signal and outputting a bus signal and a complementary bus signal to the memory cell, wherein the write drive circuit is coupled to the write enable circuit; Wherein the write enable circuit is to initiate a write operation to write data to the memory cell based on a falling edge of the write enable signal.
2. 2. The device of claim 1, wherein the write enable circuit is to initiate a write operation to write data to the memory cell based on a falling edge of the write enable signal when a supply voltage to the write drive circuit is below a first threshold voltage.
3. 3. The device of claim 2, wherein the write enable circuit is to initiate a write operation to write data to the memory cell based on a rising edge of the write enable signal when a supply voltage to the write drive circuit is above a second threshold voltage.
4. 4. The device of claim 3, wherein a time to write the data to the memory cell based on the falling edge is configurable based on a pulse width of the write enable signal.
5. 5. The device of claim 3, wherein the first threshold voltage is about 0.5 volts and the second threshold voltage is about 0.8 volts.
6. 6. The device of claim 1, wherein the write enable circuit comprises: A first NMOS transistor having a gate terminal for receiving the write enable signal, a source terminal, and a drain terminal coupled to the source terminal, and A second NMOS transistor having a gate terminal for receiving the write enable signal, a source terminal coupled to ground, and a drain terminal coupled to the drain terminal of the first NMOS transistor.
7. 7. The device of claim 6, wherein the write drive circuit comprises a first CMOS inverter for receiving the data signal and a second CMOS inverter for receiving the complementary data signal.
8. 8. The apparatus of claim 7, wherein the first CMOS inverter is to output the complementary bus signal and the second CMOS inverter is to output the bus signal.
9. 9. The device of claim 8, wherein the write enable circuit is coupled to the first CMOS inverter to place the complementary bus signal at a negative voltage based on the falling edge of the write enable signal.
10. 10. The apparatus of claim 9, wherein the drain terminal of the first NMOS transistor is coupled to the drain terminal of the second NMOS transistor, and the drain terminals of the first and second NMOS transistors are coupled to the first and second CMOS inverters.
11. 11. The apparatus of claim 7, wherein the first CMOS inverter comprises a first PMOS transistor and a third NMOS transistor and the second CMOS inverter comprises a second PMOS transistor and a fourth NMOS transistor.
12. 12. The apparatus of claim 11, wherein the first PMOS transistor of the first CMOS inverter comprises a source terminal coupled to a supply voltage, a gate terminal coupled to the data signal, and a drain terminal coupled to the complementary bus signal, and the third NMOS transistor of the first CMOS inverter comprises a drain terminal coupled to the complementary bus signal, a gate terminal coupled to the data signal, and a source terminal coupled to the write enable circuit.
13. 13. The apparatus of claim 12, wherein the second PMOS transistor of the second CMOS inverter comprises a source terminal coupled to the supply voltage, a gate terminal coupled to the complementary data signal, and a drain terminal coupled to the bus signal, and the fourth NMOS transistor of the second CMOS inverter comprises a drain terminal coupled to the bus signal, a gate terminal coupled to the complementary data signal, and a source terminal coupled to the write enable circuit.
14. 14. The apparatus of claim 13, wherein the drain terminals of the first and second NMOS transistors are coupled to the source terminals of the third and fourth NMOS transistors.
15. 15. A method of writing data to a memory cell, the method comprising: generating a write enable signal to control writing of data to the memory cell; receiving a data signal and a complementary data signal corresponding to the data to be written to the memory cell; Outputting a bus signal and a complementary bus signal based on the write enable signal, the data signal, and the complementary data signal; the data is stored in the memory cells based on a falling edge of the write enable signal.
16. 16. The method of claim 15, wherein the data is stored in the memory cell based on a falling edge of the write enable signal when a supply voltage is below a first threshold voltage.
17. 17. The method of claim 16, wherein the data is stored in the memory cell based on a rising edge of the write enable signal when a supply voltage is above a second threshold voltage.
18. 18. The method of claim 17, the method comprising adjusting a pulse width of the write enable signal based on the falling edge of the write enable signal to control writing data to the memory cell.
19. 19. The method of claim 17, wherein the first threshold voltage is about 0.5 volts and the second threshold voltage is about 0.8 volts.
20. 20. The method of claim 17, wherein the first threshold voltage is approximately equal to the second threshold voltage.

Description

Method and apparatus for dual edge memory write operation Cross Reference to Related Applications The present application claims priority from U.S. provisional patent application No. 63/544,109, filed on day 13 of 10 in 2023, and U.S. non-provisional patent application No. 18/914,119, filed on day 12 of 10 in 2024, the contents of which are hereby incorporated by reference in their entireties. Technical Field The present disclosure relates generally to memory write operations, and more particularly to memory write operations that use rising and falling edges to initiate write operations. Disclosure of Invention According to one aspect of one or more examples, an apparatus is provided that may include a write enable circuit to receive a write enable signal to write data to a memory cell, and a write drive circuit to receive a data signal and a complementary data signal and output a bus signal and a complementary bus signal to the memory cell, wherein the write drive circuit is coupled to the write enable circuit. The write enable circuit may initiate a write operation to write data to the memory cell based on a falling edge of the write enable signal. The write enable circuit may initiate a write operation to write data to the memory cell based on a falling edge of the write enable signal when a supply voltage to the write drive circuit is below a first threshold voltage. The write enable circuit may initiate a write operation to write data to the memory cell based on a rising edge of the write enable signal when a supply voltage to the write drive circuit is above a second threshold voltage. The first threshold voltage may be about 0.5 volts and the second threshold voltage may be about 0.8 volts. The write enable circuit may include a first NMOS transistor having a gate terminal for receiving a write enable signal, a source terminal, and a drain terminal coupled to the source terminal, and a second NMOS transistor having a gate terminal for receiving the write enable signal, a source terminal coupled to ground, and a drain terminal coupled to the drain terminal of the first NMOS transistor. The gate driving circuit may include a first CMOS inverter for receiving a data signal and a second CMOS inverter for receiving a complementary data signal. The first CMOS inverter may output a complementary bus signal and the second CMOS inverter may output a bus signal. The write enable circuit may be coupled to the first CMOS inverter to place the complementary bus signal at a negative voltage based on a falling edge of the write enable signal. The drain terminal of the first NMOS transistor may be coupled to the drain terminal of the second NMOS transistor, and the drain terminals of the first and second NMOS transistors may be coupled to the first and second CMOS inverters. The first CMOS inverter may include a first PMOS transistor and a third NMOS transistor, and the second CMOS inverter may include a second PMOS transistor and a fourth NMOS transistor. The first PMOS transistor of the first CMOS inverter may include a source terminal coupled to the supply voltage, a gate terminal coupled to the data signal, and a drain terminal coupled to the complementary bus signal, and the third NMOS transistor of the first CMOS inverter may include a drain terminal coupled to the complementary bus signal, a gate terminal coupled to the data signal, and a source terminal coupled to the write enable circuit. The second PMOS transistor of the second CMOS inverter may include a source terminal coupled to the supply voltage, a gate terminal coupled to the complementary data signal, and a drain terminal coupled to the bus signal, and the fourth NMOS transistor of the second CMOS inverter may include a drain terminal coupled to the bus signal, a gate terminal coupled to the complementary data signal, and a source terminal coupled to the write enable signal. Drain terminals of the first NMOS transistor and the second NMOS transistor are coupled to source terminals of the third NMOS transistor and the fourth NMOS transistor. According to one aspect of one or more examples, a method of writing data to a memory cell is provided. The method may include generating a write enable signal to control writing of data to the memory cell, receiving a data signal and a complementary data signal corresponding to data to be written to the memory cell, outputting a bus signal and a complementary bus signal based on the write enable signal, the data signal and the complementary data signal, and storing the data in the memory cell based on a falling edge of the write enable signal. When the supply voltage is lower than the first threshold voltage, data may be stored in the memory cell based on a falling edge of the write enable signal. When the supply voltage is higher than the second threshold voltage, data may be stored in the memory cell based on a rising edge of the write enable signal. The method may further include adjusting a pulse width of th