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CN-122029742-A - Quasi adiabatic logic

CN122029742ACN 122029742 ACN122029742 ACN 122029742ACN-122029742-A

Abstract

Apparatus and associated methods relate to a quasi-adiabatic circuit that includes a plurality of quasi-adiabatic logic gates that are daisy-chained in a phased sequence. Each of the quasi-adiabatic logic gates in the daisy-chained sequence has a power node conductively coupled to one of the sinusoidal power signals in the phased sequence of sinusoidal power signals. The sinusoidal power signal conductively coupled to each of the quasi-adiabatic logic gates is phase-delayed relative to the sinusoidal power signal conductively coupled to its immediately preceding quasi-adiabatic logic gate in the daisy-chained sequence. The phase delay is equal to 360 ° divided by the number of sinusoidal power signals in the phased sequence of sinusoidal power signals.

Inventors

  • James. Lupino
  • Tommy Forrest Gump

Assignees

  • QAL半导体有限公司

Dates

Publication Date
20260512
Application Date
20241007
Priority Date
20231005

Claims (20)

  1. 1. A quasi-adiabatic logic circuit, comprising: A sinusoidal power generation circuit configured to generate a plurality of sinusoidal power signals having a common frequency and evenly distributed over 360 ° of phase in a modular phasing sequence, each sinusoidal power signal of the plurality of sinusoidal power signals having a phase with a phase lag phase difference angle relative to a previous one of the modular phasing sequence And advancing the phase difference angle relative to the phase of the latter of the molded phase sequences And (C) sum A plurality of quasi-adiabatic logic gates daisy-chained in an "output to input" manner, each quasi-adiabatic logic gate of the plurality of quasi-adiabatic logic gates being powered by a corresponding sinusoidal power signal of the plurality of sinusoidal power signals, each quasi-adiabatic logic gate of the plurality of quasi-adiabatic logic gates comprising: One or more logic input terminals configured to receive one or more corresponding logic input signals, and A logic output terminal configured to provide a logic output signal, wherein the logic output signal is characterized by a phase of a corresponding sinusoidal power signal of the plurality of sinusoidal power signals providing power to the plurality of quasi-adiabatic logic gates.
  2. 2. The quasi-adiabatic logic circuit of claim 1, wherein each quasi-adiabatic logic gate of the plurality of quasi-adiabatic logic gates is configured to receive one or more corresponding logic input signals characterized by a phase that is advanced by a phase difference angle relative to a phase characterizing a logic output signal provided by the quasi-adiabatic logic gate 。
  3. 3. The quasi-adiabatic logic circuit of claim 1, wherein the plurality of sinusoidal power signals is an even number N of sinusoidal power signals, thereby defining a phase difference angle 360 °/N.
  4. 4. The quasi-adiabatic logic circuit of claim 3, wherein the plurality of sinusoidal power signals is four or more sinusoidal power signals, each sinusoidal power signal having a phase that is different from the phase of other sinusoidal power signals in the plurality of sinusoidal power signals.
  5. 5. The quasi-adiabatic logic circuit of claim 4, wherein the plurality of sinusoidal power signals is eight or more sinusoidal power signals, each sinusoidal power signal having a phase that is different from the phase of other sinusoidal power signals in the plurality of sinusoidal power signals.
  6. 6. The quasi-adiabatic logic circuit of claim 3, wherein each of the first half 1-2-1 of the even number N of sinusoidal power signals is complementary to a corresponding sinusoidal power signal of the second half N/2-N of the even number of sinusoidal power signals.
  7. 7. A quasi-adiabatic logic circuit as set forth in claim 3, wherein each phase And phase of Complementary.
  8. 8. The quasi-adiabatic logic circuit of claim 7, wherein the complementary phases are 180 ° out of phase with each other.
  9. 9. The quasi-adiabatic logic circuit of claim 3, wherein each quasi-adiabatic logic gate of the plurality of quasi-adiabatic logic gates has a logic resolution phase that occurs in response to a sinusoidal power signal providing power to the quasi-adiabatic logic gate having a first polarity.
  10. 10. The quasi-adiabatic logic circuit of claim 9, wherein during the logic parsing phase, an output signal provided by the quasi-adiabatic logic gate indicates a logic function for which the quasi-adiabatic logic gate is configured.
  11. 11. The quasi-adiabatic logic circuit of claim 5, wherein the phase difference angle Less than or equal to 120 deg..
  12. 12. The quasi-adiabatic logic circuit of claim 5, wherein the phase difference angle Less than or equal to 90 deg..
  13. 13. The quasi-adiabatic logic circuit of claim 1, wherein each quasi-adiabatic logic gate of the plurality of quasi-adiabatic logic gates is a quasi-adiabatic logic gate.
  14. 14. The quasi-adiabatic logic circuit of claim 13, wherein each quasi-adiabatic logic gate in the phased sequence of quasi-adiabatic logic gates comprises: A pull-up network including one or more pull-up transistors configured to perform a pull-up logic function, each pull-up transistor of the one or more pull-up transistors of the pull-up network having a control node coupled to one of the one or more logic input terminals, the pull-up network configured to adjust a conductance between a first power node and the logic output terminal based on the pull-up logic function the pull-up network is configured to perform and a logic input signal received on the one or more logic input terminals, and A pull-down network comprising one or more pull-down transistors configured to perform a pull-down logic function complementary to the pull-up logic function, each pull-down transistor of the pull-down network having a control node coupled to one of the one or more logic input terminals, the pull-down network configured to adjust a conductance between a second power node and the logic output terminal based on the pull-down logic function the pull-down network is configured to perform and a logic input signal received on the logic input terminal.
  15. 15. The quasi-adiabatic logic circuit of claim 14, wherein a peak-to-peak amplitude of each sinusoidal power signal of the plurality of sinusoidal power signals is less than a sum V THN + V THP of threshold voltages of pull-up and pull-down transistors of the plurality of quasi-adiabatic logic gates.
  16. 16. The quasi-adiabatic logic circuit of claim 14, wherein the pull-up transistor comprises PMOS transistors, each PMOS transistor having a body node driven by one of the plurality of sinusoidal power signals.
  17. 17. The quasi-adiabatic logic circuit of claim 14, wherein the pull-up transistors comprise PMOS transistors, each PMOS transistor having a body node biased by a sinusoidal signal that keeps a parasitic junction of the body reverse biased.
  18. 18. The quasi-adiabatic logic circuit of claim 14, wherein the pull-down transistors comprise NMOS transistors, each NMOS transistor having a body node driven by one of the plurality of sinusoidal power signals.
  19. 19. The quasi-adiabatic logic circuit of claim 13, wherein the pull-down transistors comprise NMOS transistors, each NMOS transistor having a body node biased by a sinusoidal signal that keeps a parasitic junction of the body reverse biased.
  20. 20. The quasi-adiabatic logic circuit of claim 1, further comprising: A plurality of tuning capacitors selectively coupled across power terminals receiving operating power for the quasi-adiabatic logic circuit, and A tuning controller selectively couples one or more selected tuning capacitors of the plurality of tuning capacitors across the power terminal, the one or more selected tuning capacitors selected such that a resonant frequency f RESONANCE of a tank circuit comprising an inductor conductively coupled across the power terminal is substantially equal to a frequency f POWER of one of the phased sequences of sinusoidal power signals provided across the power terminal.

Description

Quasi adiabatic logic Cross Reference to Related Applications The present application is a non-provisional application claiming the benefit of U.S. provisional application serial No. 63/588,259 filed by j.lupino and t.agan at 5 of 10 of 2023, entitled "QUASI-ADIABATIC LOGIC". Background Conventional CMOS logic is powered between two DC power buses. The CMOS logic circuit is configured to perform a specific logic function based on the input signal received thereby. When the input signal changes, the output signal of the CMOS logic gate changes state. During transitions of the varying input signal, the CMOS logic gate may conduct high peak amplitude current pulses. These current pulses occur due to at least two different phenomena, crowbar current and capacitive charging. First, if both the pull-up and pull-down networks of CMOS logic gates are at least partially on, then these pull-up and pull-down networks provide a path for current to flow directly from one power supply to the other. This phenomenon is known as "crowbar current". Second, each node that changes state needs to charge the capacitance of that node. Of these two phenomena, crowbar current is the most severe because it does not have any useful purpose. Unlike crowbar currents, the current used to charge the parasitic capacitance of the subsequent logic gate is used to change the voltage of these nodes, which is required to perform the logic function of the CMOS logic gate. Crowbar current is undesirable for a number of reasons. First, crowbar current is a significant source of power consumption for CMOS logic gates. Second, current pulses that charge the output node, especially those with high peak current amplitudes, can cause the power supply to collapse instantaneously. Third, these pulses are sources of noise that can cause errors in the function of circuits using such CMOS logic gates. Various adiabatic logic circuits have been proposed to address such problems associated with conventional CMOS logic gates. These adiabatic logic circuits have been shown to reduce the power consumption of the logic circuitry, as well as the amplitude of the current pulses. Many of the proposed adiabatic logic techniques require reversible circuitry, which in effect doubles the number of transistors required to perform the logic function. This in turn reduces any power reduction and increases costs due to the increase in die size. Reducing the clock rate may further reduce power consumption, but such a reduction in clock rate may significantly increase the cost of performing the calculations. Disclosure of Invention Some embodiments relate to a quasi-adiabatic logic circuit including a sinusoidal power generation circuit and a plurality of quasi-adiabatic logic gates. The sinusoidal power generation circuit is configured to generate a plurality of sinusoidal power signals having a common frequency that are evenly distributed over 360 ° in a modular phasing sequence (modulo phased sequence). Each sinusoidal power signal of the plurality of sinusoidal power signals has a phase that lags behind a phase difference angle relative to a previous one of the modular phase sequencesAnd phase advance phase difference angle relative to the latter of the modular phase sequences. A plurality of quasi-adiabatic logic gates are daisy-chained with an "output to input" (day-chain connected output-to-input). Each quasi-adiabatic logic gate of the plurality of quasi-adiabatic logic gates is powered by a corresponding sinusoidal power signal of the plurality of sinusoidal power signals. Each quasi-adiabatic logic gate of the plurality of quasi-adiabatic logic gates includes i) one or more logic input terminals configured to receive one or more corresponding logic input signals, and ii) a logic output terminal configured to provide a logic output signal, wherein the logic output signal is characterized by a phase of a corresponding sinusoidal power signal of a plurality of sinusoidal power signals providing power to the plurality of quasi-adiabatic logic gates. Drawings Fig. 1 is a schematic diagram of an example of a quasi-adiabatic logic circuit. Fig. 2 is a graph depicting the voltage/time relationship of sinusoidal power signals V A to V H. FIG. 3 is a graph of an example output signal generated by a quasi-adiabatic logic gate operatively powered by a sinusoidal power signal. Fig. 4 is a schematic diagram of a method for automatically tuning the capacitance of a tank circuit of an AC power source. Fig. 5 is a schematic diagram of two sequential quasi-adiabatic inverters. Fig. 6 is a schematic diagram of two sequential quasi-adiabatic inverters in which the body regions are biased to the respective sources. Fig. 7A is a schematic diagram of a semiconductor chip and an AC power supply configured in a quasi-adiabatic manner. Fig. 7B is a schematic diagram of a semiconductor chip and an AC power supply and transformer configured in a quasi-adiabatic manner. Fig. 7C is a schematic