CN-122029743-A - System and method for weight sequential irregular error correction code construction

CN122029743ACN 122029743 ACN122029743 ACN 122029743ACN-122029743-A

Abstract

A non-transitory computer readable medium and associated method include processing circuitry to perform an ordered error correction code construction. The processing circuit receives a first plurality of matrices. The processing circuit is to generate a second plurality of matrices based on the at least one additive candidate matrix and each respective matrix of the first plurality of matrices. The processing circuit then generates a third plurality of matrices based on the at least one additive test matrix and each respective matrix of the second plurality of matrices. Each respective weight indicative of a respective extensibility of each matrix of the second plurality of matrices is determined based on the third plurality of matrices. The processing circuit then selects at least one matrix from the second plurality of matrices based on the determined weights. The processing circuit then generates an error correction code based on one of the at least one selected matrix.

Inventors

Y.H.Chi

Assignees

爱思开海力士存储器产品解决方案公司(以”Solidigm”名称运营)

Dates

Publication Date: 20260512
Application Date: 20240530
Priority Date: 20230823

Claims (20)

1.A method, comprising: (a) Receiving, using a processing circuit, a first plurality of matrices; (b) Generating, using the processing circuitry, a second plurality of matrices based on the at least one additive candidate matrix and each respective matrix of the first plurality of matrices; (c) Generating, using the processing circuitry, a third plurality of matrices based on the at least one additive test matrix and each respective matrix of the second plurality of matrices; (d) Determining respective weights indicative of respective extensibility of each matrix of the second plurality of matrices based on the third plurality of matrices; (e) Selecting at least one matrix from the second plurality of matrices based on the weights of the second plurality of matrices using the processing circuit, and (F) An error correction code is generated based on one of the at least one selected matrix using processing circuitry.
2. The method of claim 1, wherein generating a second plurality of matrices based on at least one additive candidate matrix and each respective matrix of the first plurality of matrices comprises: Generating at least one additive candidate matrix, and For each additive candidate matrix, a second plurality of matrices is generated by adding a respective additive candidate matrix of the at least one additive candidate matrix to each respective matrix of the first plurality of matrices.
3. The method of claim 1, wherein generating a third plurality of matrices based on at least one additive test matrix and each respective matrix of the second plurality of matrices comprises: Generating at least one additive test matrix, each additive test matrix comprising: A number of rows corresponding to the number of rows of each of the first plurality of matrices, and A number of columns that is less than a number of columns of each of the first plurality of matrices.
4. The method of claim 1, wherein generating a third plurality of matrices based on at least one additive test matrix and each respective matrix of the second plurality of matrices comprises: For each additive test matrix, a third plurality of matrices is generated by appending a respective additive test matrix of the at least one additive test matrix to each respective matrix of the second plurality of matrices.
5. The method of claim 1, wherein generating a third plurality of matrices based on at least one additive test matrix and each respective matrix of the second plurality of matrices comprises: for each additive test matrix, a third plurality of matrices is generated by replacing a portion of each respective matrix in the second plurality of matrices with the respective additive test matrix.
6. The method of claim 1, wherein determining, based on the third plurality of matrices, respective weights indicative of respective extensibility of each matrix of the second plurality of matrices comprises: Calculating for each respective matrix of the third plurality of matrices a respective number of association rings of at most a predetermined length, and Weights for each respective matrix of the second plurality of matrices are determined based on the respective calculated number of association rings of at most a predetermined length.
7. The method of claim 6, wherein calculating a respective number of association rings of at most a predetermined length for each respective matrix of the third plurality of matrices comprises: Generating a corresponding Tanner graph representing a corresponding matrix, and The number of associated rings of at most a predetermined length in the corresponding Tanner graph is determined.
8. The method of claim 7, wherein determining the number of associated rings of at most a predetermined length in the respective Tanner graph comprises evaluating the associated rings of at most a predetermined length by using a Fossorier condition of the respective Tanner graph.
9. The method of claim 6, wherein determining weights for each respective matrix of the second plurality of matrices based on the respective calculated number of association rings of at most a predetermined length comprises: weights for respective ones of the second plurality of matrices are determined based on the calculated number of association loops of at most a predetermined length for each of the third plurality of matrices generated based on the respective ones of the second plurality of matrices.
10. The method of claim 1, wherein selecting at least one matrix from the second plurality of matrices based on the weights of the second plurality of matrices comprises selecting at least one matrix from the second plurality of matrices, wherein the selected matrix corresponds to a maximum weight among the determined weights.
11. The method of claim 1, further comprising repeating (a) - (f) a predetermined number of iterations.
12. A non-transitory computer-readable medium having non-transitory computer-readable instructions encoded thereon, which when executed by a processing circuit, cause the processing circuit to: (a) Receiving a first plurality of matrices; (b) Generating a second plurality of matrices based on the at least one additive candidate matrix and each respective matrix of the first plurality of matrices; (c) Generating a third plurality of matrices based on the at least one additive test matrix and each respective matrix of the second plurality of matrices; (d) Determining respective weights indicative of respective extensibility of each matrix of the second plurality of matrices based on the third plurality of matrices; (e) Selecting at least one matrix from the second plurality of matrices based on the weights of the second plurality of matrices, and (F) An error correction code is generated based on one of the at least one selected matrix.
13. The non-transitory computer-readable medium of claim 12, wherein to generate the second plurality of matrices based on the at least one additive candidate matrix and each respective matrix of the first plurality of matrices, the processing circuit is to: Generating at least one additive candidate matrix, and For each additive candidate matrix, a second plurality of matrices is generated by adding a respective additive candidate matrix of the at least one additive candidate matrix to each respective matrix of the first plurality of matrices.
14. The non-transitory computer-readable medium of claim 12, wherein to generate a third plurality of matrices based on the at least one additive test matrix and each respective matrix of the second plurality of matrices, the processing circuit is to: Generating at least one additive test matrix, each additive test matrix comprising: A number of rows corresponding to the number of rows of each of the first plurality of matrices, and A number of columns that is less than a number of columns of each of the first plurality of matrices.
15. The non-transitory computer-readable medium of claim 12, wherein to generate a third plurality of matrices based on the at least one additive test matrix and each respective matrix of the second plurality of matrices, the processing circuit is to: For each additive test matrix, a third plurality of matrices is generated by appending a respective additive test matrix of the at least one additive test matrix to each respective matrix of the second plurality of matrices.
16. The non-transitory computer-readable medium of claim 12, wherein to generate a third plurality of matrices based on the at least one additive test matrix and each respective matrix of the second plurality of matrices, the processing circuit is to: for each additive test matrix, a third plurality of matrices is generated by replacing a portion of each respective matrix in the second plurality of matrices with the respective additive test matrix.
17. The non-transitory computer-readable medium of claim 12, wherein to determine respective weights indicative of respective extensibility of each matrix of the second plurality of matrices based on the third plurality of matrices, the processing circuitry is to: Calculating for each respective matrix of the third plurality of matrices a respective number of association rings of at most a predetermined length, and Weights for each respective matrix of the second plurality of matrices are determined based on the respective calculated number of association rings of at most a predetermined length.
18. The non-transitory computer-readable medium of claim 17, wherein to calculate a respective number of association loops of at most a predetermined length for each respective matrix of the third plurality of matrices, the processing circuit is to: Generating a corresponding Tanner graph representing a corresponding matrix, and The number of associated rings of at most a predetermined length in the corresponding Tanner graph is determined.
19. The non-transitory computer-readable medium of claim 18, wherein to determine the number of associated rings of at most a predetermined length in the respective Tanner graph, the processing circuit is to evaluate the associated rings of at most a predetermined length by using a Fossorier condition of the respective Tanner graph.
20. The non-transitory computer-readable medium of claim 17, wherein to determine weights for each respective matrix of the second plurality of matrices based on a respective calculated number of association loops of at most a predetermined length, the processing circuit is to: weights for respective ones of the second plurality of matrices are determined based on the calculated number of association loops of at most a predetermined length for each of the third plurality of matrices generated based on the respective ones of the second plurality of matrices.

Description

System and method for weight sequential irregular error correction code construction Technical Field The present disclosure relates to systems and methods for constructing error correction codes. Disclosure of Invention In accordance with the present disclosure, systems and methods are provided for performing ordered error correction code construction based on respective corresponding weights of a plurality of generated matrices. The systems and methods disclosed herein enable ordered error correction code (e.g., low Density Parity Check (LDPC) code) construction based on respective corresponding weights of a plurality of generated matrices. Such an ordered error correction code construction improves the error floor (error floor) of the constructed error correction code by reducing the number of associated rings (INCIDENT CYCLE) in the matrix used in the error correction code construction, wherein the reduced associated rings have at most a predetermined length, which may lead to error correction code failure. A matrix containing many association rings may lead to an unexpected increase in error correction code failure rate, even when transmitted over a bus or channel with little noise, and thus increase the error floor of the constructed error correction code. In order to reduce the error floor of bit errors during error correction code construction, an association ring of up to a predetermined length should be avoided or removed from the matrix by matrix manipulation. In some embodiments, the predetermined length corresponds to a length of an associated ring that results in a greater error correction code failure rate than a length longer than the predetermined length. The ordered error correction code construction of the present disclosure is dependent on a predetermined length such that at most an associated ring of the predetermined length will be evaluated and reduced or avoided. In some embodiments, a system (e.g., a server device or a storage device) is equipped with memory and processing circuitry communicatively coupled to each other. In some embodiments, the processing circuit generates a first plurality of matrices based on the random number, wherein each matrix has a predetermined size. In some embodiments, the processing circuit generates a second plurality of matrices based on at least one additive candidate matrix and each respective matrix of the first plurality of matrices, wherein each respective matrix of the second plurality of matrices has a respective weight indicative of scalability of the respective matrix. Scalability of the respective matrix may be defined as a characteristic that indicates the ability of the matrix to be used for further iterations of the ordered error correction code construction. In some embodiments, the processing circuit then generates a third plurality of matrices based on the at least one additive test matrix and each respective matrix of the second plurality of matrices. The processing circuitry then determines a weight for each respective matrix of the second plurality of matrices and selects at least one matrix based on the weight relative to other weights of the matrices of the second plurality of matrices. In some embodiments, at least one matrix selected from the second plurality of matrices becomes the updated first plurality of matrices for further ordered error correction code construction. In some embodiments, the processing circuit repeats the process a predetermined number of iterations to select at least one selected matrix. Once the processing circuit selects at least one matrix, the processing circuit generates an error correction code based on one of the at least one selected matrix. In some embodiments, error correction codes (e.g., LDPC codes) are used to detect signal channel reliability issues. Drawings The following description includes a discussion of the figures having illustrations given by way of example of implementations of embodiments of the present disclosure. The drawings are to be understood by way of example and not by way of limitation. As used herein, references to one or more "embodiments" should be understood to describe particular features, structures, and/or characteristics that may be included in at least one embodiment. Thus, phrases such as "in one embodiment" or "in an alternative embodiment" appearing herein describe various embodiments and implementations, and do not necessarily all refer to the same embodiment. However, they are not necessarily mutually exclusive. FIG. 1 shows an illustrative diagram of a system of an electronic device having processing circuitry and memory, according to some embodiments of the present disclosure; FIG. 2 is a flowchart of illustrative steps for generating an error correction code having an ordered code structure in accordance with some embodiments of the present disclosure; FIG. 3 shows a flowchart of illustrative steps of a sub-process for generating a first plurality of matrice