CN-122029941-A - Capacitor built-in substrate

CN122029941ACN 122029941 ACN122029941 ACN 122029941ACN-122029941-A

Abstract

The capacitor-built-in substrate (1) comprises a core layer (10) which comprises at least one layer of core material (11) provided with a cavity (11X) in the thickness direction, a capacitor element (20) which is internally provided with the cavity (11X) of the core material (11), and a through conductor (30) which is arranged in a manner of penetrating the core layer (10) in the thickness direction. The feedthrough conductor (30) includes a1 st feedthrough conductor (31) that is provided so as to pierce the capacitor element (20) in the core layer (10) and is electrically connected to the load (50) and the power supply (55), and a 2 nd feedthrough conductor (32) that is provided so as to pierce the capacitor element (20) in the core layer (10) at a position separate from the 1 st feedthrough conductor (31) and is electrically connected to the load (50) and the power supply (55). The 1 st through conductor (31) is electrically connected to the 1 st electrode (21) of the capacitor element (20). The 2 nd through conductor (32) is electrically connected to a 2 nd electrode (22) of a different polarity from the 1 st electrode (21) of the capacitor element (20).

Inventors

TAKAHASHI AKITOMO
HIMEDA KOSHI
YAMADA SHUUHEI

Assignees

株式会社村田制作所

Dates

Publication Date: 20260512
Application Date: 20240919
Priority Date: 20231018

Claims (13)

1. A capacitor built-in substrate, wherein, The capacitor built-in substrate includes: A core layer including at least one layer of a core material having a cavity in a thickness direction; a capacitor element built in the cavity of the core material, and A penetrating conductor provided so as to penetrate the core layer in the thickness direction, The feedthrough conductors include a1 st feedthrough conductor provided so as to pass through the capacitor element in the core layer and electrically connect to a load and a power source, and a2 nd feedthrough conductor provided so as to pass through the capacitor element in the core layer at a position separate from the 1 st feedthrough conductor and electrically connect to the load and the power source, The 1 st through conductor is electrically connected to the 1 st electrode of the capacitor element, The 2 nd via conductor is electrically connected to a2 nd electrode having a polarity different from that of the 1 st electrode of the capacitor element.
2. The capacitor built-in substrate according to claim 1, wherein, The through conductors further include a 3 rd through conductor provided so as not to pass through the capacitor element in the core layer and pass through the core material, and electrically connected to the interface and the load.
3. The capacitor built-in substrate according to claim 2, wherein, The core layer has a1 st main face and a2 nd main face opposed in the thickness direction, The 1 st through conductor and the 2 nd through conductor are electrically connected to the load at the 1 st main surface side end and electrically connected to the power supply at the 2 nd main surface side end, The 3 rd through conductor is electrically connected to the load at an end on the 1st principal surface side and is electrically connected to the interface at an end on the 2nd principal surface side.
4. The capacitor built-in substrate according to claim 3, wherein, The 3 rd through conductor is disposed on the outer peripheral side of the 1 st through conductor and the 2 nd through conductor when viewed from above in the thickness direction.
5. The capacitor built-in substrate according to claim 1, wherein, The core layer has a1 st main face and a2 nd main face opposed in the thickness direction, The 1 st through conductor and the 2 nd through conductor are electrically connected to the load at the 1 st main surface side end and electrically connected to the power supply at the 2 nd main surface side end.
6. The capacitor built-in substrate according to any one of claim 3 to 5, wherein, The 1 st through conductor and the 2 nd through conductor are electrically connected to the load directly below the load.
7. The capacitor built-in substrate according to any one of claims 1 to 6, wherein, The same layer of the core material has a plurality of the chambers, The capacitor elements are respectively built in the chambers.
8. The capacitor built-in substrate according to any one of claims 1 to 7, wherein, The core layer comprises a plurality of layers of the core material in the thickness direction, At least one layer of the core material has the cavity.
9. The capacitor built-in substrate according to claim 8, wherein, More than two of the layers of the core material have the chambers, The capacitor elements are respectively built in the chambers.
10. The capacitor built-in substrate according to claim 9, wherein, The capacitor element includes a1 st capacitor element and a2 nd capacitor element respectively built in the chambers of the core material of different layers, The 1 st feedthrough conductor is provided so as to be feedthrough to the 1 st capacitor element and electrically connected to the 1 st electrode of the 1 st capacitor element, and is provided so as to be feedthrough to the 2 nd capacitor element and electrically connected to the 1 st electrode of the 2 nd capacitor element having the same polarity as the 1 st electrode of the 1 st capacitor element, The 2 nd feedthrough conductor is provided so as to be feedthrough in the 1 st capacitor element and electrically connected to the 2 nd electrode of the 1 st capacitor element, and is provided so as to be feedthrough in the 2 nd capacitor element and electrically connected to the 2 nd electrode of the 2 nd capacitor element having the same polarity as the 2 nd electrode of the 1 st capacitor element.
11. The capacitor built-in substrate according to claim 9, wherein, The capacitor element includes a1 st capacitor element and a2 nd capacitor element respectively built in the chambers of the core material of different layers, The via conductors further include a 4 th via conductor provided so as to penetrate the capacitor element in the core layer at a position separated from the 1 st via conductor and the 2 nd via conductor, The 1 st feedthrough conductor is provided so as to be continuous with the 1 st electrode of the 1 st capacitor element and electrically connected to the 1 st electrode of the 1 st capacitor element, and is provided so as to be continuous with the 2 nd capacitor element and electrically connected to neither the 1 st electrode of the 2 nd capacitor element having the same polarity as the 1 st electrode of the 1 st capacitor element nor the 2 nd electrode of the 2 nd capacitor element having the same polarity as the 2 nd electrode of the 1 st capacitor element, The 2 nd feedthrough conductor is provided so as to be feedthrough in the 1 st capacitor element and electrically connected to the 2 nd electrode of the 1 st capacitor element, and is provided so as to be feedthrough in the 2 nd capacitor element and electrically connected to the 1 st electrode of the 2 nd capacitor element, The 4 th feedthrough conductor is provided so as to extend through the 1 st capacitor element and is electrically connected to neither the 1 st electrode nor the 2 nd electrode of the 1 st capacitor element, and is provided so as to extend through the 2 nd capacitor element and is electrically connected to the 2 nd electrode of the 2 nd capacitor element.
12. The capacitor built-in substrate according to any one of claims 1 to 11, wherein, The plurality of capacitor elements are disposed in the cavity of the core material of the same layer in the thickness direction.
13. The capacitor built-in substrate according to any one of claims 1 to 12, wherein, The capacitor element includes a capacitor portion and a sealing layer provided so as to cover at least one main surface of the capacitor portion, The capacitor part includes an anode plate having a porous part on at least one main surface of a core part, a dielectric layer provided on a surface of the porous part, and a cathode layer provided on a surface of the dielectric layer.

Description

Capacitor built-in substrate Technical Field The present invention relates to a capacitor built-in substrate. Background Patent document 1 discloses a printed circuit board with built-in chips, which includes a central layer formed with through holes and voids, and composed of chips inserted into the voids and fixed by plating and circuit patterns formed on both surfaces, an insulating layer laminated on one or both surfaces of the central layer and including the through holes filled with conductive ink, and a circuit layer laminated on the insulating layer and formed with the circuit patterns and the through holes electrically connected to the plating layer of the central layer via the through holes. In patent document 1, a chip-built-in printed circuit board is defined such that, in a state in which a chip (for example, a capacitor) is embedded in an inner layer or an outer portion of the board itself, the chip and a portion of the printed circuit board are combined, regardless of the size of the board itself, and such a board is referred to as a "chip-built-in" printed circuit board. Prior art literature Patent literature Patent document 1 Japanese patent application No. 4061318 Disclosure of Invention Problems to be solved by the invention For example, in the case of applying the substrate with a capacitor incorporated therein to a semiconductor package substrate as the chip-built-in printed circuit board described in patent document 1, if the power supply to the computing device as an example of the load is increased, there is a possibility that the signal quality is deteriorated due to power supply noise. In order to suppress such degradation of signal quality due to power supply noise, it is necessary to reduce loop impedance between the load and the power supply. The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a capacitor-built-in substrate capable of reducing loop impedance between a load and a power supply and suppressing degradation of signal quality due to power supply noise. Solution for solving the problem The substrate for a built-in capacitor comprises a core layer comprising at least one layer of core material having a cavity in the thickness direction, a capacitor element which is arranged in the cavity of the core material, and a penetrating conductor which penetrates the core layer in the thickness direction. The through conductors include a 1 st through conductor provided so as to pass through the capacitor element in the core layer and electrically connected to a load and a power supply, and a 2 nd through conductor provided so as to pass through the capacitor element in the core layer at a position separated from the 1 st through conductor and electrically connected to the load and the power supply. The 1 st through conductor is electrically connected to the 1 st electrode of the capacitor element. The 2 nd via conductor is electrically connected to a 2 nd electrode having a polarity different from that of the 1 st electrode of the capacitor element. ADVANTAGEOUS EFFECTS OF INVENTION According to the present invention, it is possible to provide a capacitor-built-in substrate capable of reducing loop impedance between a load and a power supply and suppressing degradation of signal quality due to power supply noise. Drawings Fig. 1 is a cross-sectional view schematically showing an example of a capacitor-built-in substrate according to embodiment 1 of the present invention. Fig. 2 is an example of an equivalent circuit block diagram of the capacitor built-in substrate shown in fig. 1. Fig. 3 is a partial cross-sectional view showing the capacitor built-in substrate shown in fig. 1. Fig. 4 is an example of a plan view taken along line A-A of fig. 3. Fig. 5 is a cross-sectional view schematically showing another example of the capacitor built-in substrate according to embodiment 1 of the present invention. Fig. 6 is an example of a top view along line A-A of fig. 5. Fig. 7 is an example of a cross-sectional view of the C portion of fig. 3 enlarged. Fig. 8 is a cross-sectional view schematically showing an example of a capacitor-built-in substrate according to embodiment 2 of the present invention. Fig. 9 is an example of an equivalent circuit block diagram of the capacitor built-in substrate shown in fig. 8. Fig. 10 is another example of an equivalent circuit block diagram of the capacitor built-in substrate shown in fig. 8. Fig. 11 is a cross-sectional view schematically showing an example of a capacitor-built-in substrate according to embodiment 3 of the present invention. Fig. 12 is an example of an equivalent circuit block diagram of the capacitor built-in substrate shown in fig. 11. Fig. 13 is a cross-sectional view schematically showing an example of a capacitor built-in substrate according to embodiment 4 of the present invention. Fig. 14 is an example of an equivalent circuit block diagram of the capac