CN-122029951-A - Managing isolation structures in semiconductor devices

Abstract

The present disclosure relates to methods, devices, and systems for managing isolation structures in semiconductor devices. An exemplary semiconductor device includes a first stack of conductive layers and isolation layers extending in a first direction and alternating with each other in a second direction perpendicular to the first direction. The semiconductor device further includes a gate slit structure extending through the first stack in the second direction, and a first isolation structure extending in the first direction. The first isolation structure includes a first portion located in the first stack and a second portion located in the gate slit structure. In the second direction, the first portion has a dimension greater than a dimension of the second portion.

Inventors

• WEI JIANLAN
• HUO ZONGLIANG
• YAN CHAO
• GAO JING
• LI SIZHE
• MAO XIAOMING
• ZHAO TINGTING

Assignees

• 长江存储科技有限责任公司

Dates

Publication Date

20260512

Application Date

20240910

Claims (20)

1. 1. A semiconductor device, comprising: a first stack of conductive layers and isolation layers extending in a first direction and alternating with each other in a second direction perpendicular to the first direction; A gate slit structure extending through the first stack in the second direction, and A first isolation structure extending along the first direction, wherein the first isolation structure includes a first portion in the first stack and a second portion in the gate slit structure, wherein a dimension of the first portion is greater than a dimension of the second portion along the second direction.
2. 2. The semiconductor device of claim 1, wherein the dimension of the first portion is greater than a dimension of an isolation layer of the first stack in the second direction.
3. 3. The semiconductor device of claim 1 or 2, wherein the first isolation structure is located between two conductive layers of the first stack.
4. 4. The semiconductor device according to any one of claims 1 to 3, further comprising: A second stack of conductive layers and isolation layers extending in the first direction and alternating with each other in the second direction, wherein the second stack is adjacent to the first stack in the second direction, and A second isolation structure extending in the first direction between the first stack and the second stack.
5. 5. The semiconductor device of any one of claims 1-4, wherein the first isolation structure comprises a dielectric material or a semiconductor material.
6. 6. The semiconductor device of any one of claims 1 to 5, wherein a portion of the gate slit structure extends through the second portion of the first isolation structure, and Wherein the portion of the gate slit structure comprises a plurality of cylinders arranged along a third direction, the third direction being perpendicular to the first direction and the second direction.
7. 7. The semiconductor device of claim 6, wherein the portion of the gate slit structure further comprises a structure having a surface comprising a series of curves.
8. 8. The semiconductor device of any one of claims 1-7, wherein a surface of the gate slit structure comprises a series of curves.
9. 9. A semiconductor device, comprising: a first stack of conductive layers and isolation layers extending in a first direction and alternating with each other in a second direction perpendicular to the first direction; A channel structure extending through the first stack in the second direction; A gate slit structure extending through the first stack in the second direction, and A first isolation structure extending in the first direction, wherein the first isolation structure includes a first portion in the first stack and a second portion in the gate slit structure, Wherein a first portion of the gate slit structure is located above the first isolation structure in the second direction, wherein a size of the first portion of the gate slit structure is greater than a size of one of the channel structures in the first direction.
10. 10. The semiconductor device of claim 9, wherein a second portion of the gate slit structure extends through the first isolation structure, wherein a dimension of the second portion of the gate slit structure is greater than the dimension of the one of the channel structures along the first direction.
11. 11. The semiconductor device of claim 9 or 10, wherein the first isolation structure is located between two conductive layers of the first stack.
12. 12. The semiconductor device according to any one of claims 9 to 11, further comprising: A second stack of conductive layers and isolation layers extending in the first direction and alternating with each other in the second direction, wherein the second stack is adjacent to the first stack in the second direction, and A second isolation structure extending in the first direction between the first stack and the second stack.
13. 13. The semiconductor device of any one of claims 9 to 12, wherein the first isolation structure comprises a dielectric material or a semiconductor material.
14. 14. The semiconductor device of any one of claims 9 to 13, wherein the second portion of the gate slit structure comprises a plurality of cylinders arranged along a third direction, the third direction being perpendicular to the first and second directions.
15. 15. The semiconductor device of claim 14, wherein the second portion of the gate slit structure further comprises a structure having a surface comprising a series of curves.
16. 16. The semiconductor device of any one of claims 9 to 15, wherein a surface of the first portion of the gate slit structure comprises a series of curves.
17. 17. A method of forming a semiconductor device, comprising: Forming a first stack of conductive layers and isolation layers extending in a first direction and alternating with each other in a second direction perpendicular to the first direction; Forming a gate slit structure extending through the first stack in the second direction, and Forming an isolation structure extending along the first direction, wherein the isolation structure comprises a first portion located in the first stack and a second portion located in the gate slit structure, wherein a dimension of the first portion is greater than a dimension of the second portion along the second direction.
18. 18. The method of claim 17, further comprising: Forming a stack of dielectric layers and isolation layers alternating with each other along the second direction, wherein a size of a first one of the isolation layers is larger than a size of a second one of the isolation layers along the second direction; forming a gate line hole extending through the stack of dielectric and isolation layers, wherein the gate line hole is arranged in a third direction perpendicular to the first and second directions, and Forming a gate line space by expanding the gate line holes, wherein the gate line holes in the second isolation layer are connected to each other in the third direction to form the gate line space, and wherein at least a portion of the gate line holes in the first isolation layer are spaced apart from each other.
19. 19. The method of claim 18, wherein forming the first stack of conductive and isolation layers comprises replacing the dielectric layer of the stack with a conductive layer, and Wherein forming the gate slit structure includes filling the gate line space with a semiconductor material.
20. 20. The method of claim 18 or 19 wherein the isolation structure comprises expanding a remaining portion of the first isolation layer after the gate line hole.

Description

Managing isolation structures in semiconductor devices Technical Field The present disclosure relates to semiconductor devices and methods of manufacturing the same. Background Semiconductor devices (e.g., memory devices) may have various structures to increase the density of memory cells and lines on a chip. For example, three-dimensional (3D) memory devices are attractive due to their ability to increase array density by stacking more layers within a similar footprint. A 3D memory device typically includes a memory array of memory cells and peripheral circuitry for facilitating operation of the memory array. Disclosure of Invention The present disclosure describes methods, apparatus, systems, and techniques for managing isolation structures in semiconductor devices. One aspect of the disclosure features a semiconductor device. The semiconductor device includes a first stack of conductive layers and isolation layers extending in a first direction and alternating with each other in a second direction perpendicular to the first direction. The semiconductor device further includes a gate slit structure extending through the first stack in the second direction, and a first isolation structure extending in the first direction. The first isolation structure includes a first portion located in the first stack and a second portion located in the gate slit structure. In the second direction, the first portion has a dimension greater than a dimension of the second portion. In some embodiments, the first portion has a dimension in the second direction that is greater than a dimension of the spacer layer of the first stack. In some embodiments, the first isolation structure is located between two conductive layers of the first stack. In some embodiments, the semiconductor device further includes a second stack of conductive layers and isolation layers extending in the first direction and alternating with each other in the second direction, and a second isolation structure extending in the first direction between the first stack and the second stack. The second stack is adjacent to the first stack in a second direction. In some embodiments, the first isolation structure comprises a dielectric material or a semiconductor material. In some embodiments, a portion of the gate slit structure extends through a second portion of the first isolation structure. The portion of the gate slit structure includes a plurality of cylinders arranged along a third direction, the third direction being perpendicular to the first direction and the second direction. In some embodiments, the portion of the gate slit structure further comprises a structure having a surface comprising a series of curves. In some embodiments, the surface of the gate slit structure comprises a series of curves. Another aspect of the disclosure features a semiconductor device. The semiconductor device includes a first stack of conductive layers and isolation layers extending in a first direction and alternating with each other in a second direction perpendicular to the first direction, a channel structure extending through the first stack in the second direction, a gate slit structure extending through the first stack in the second direction, and a first isolation structure extending in the first direction. The first isolation structure includes a first portion located in the first stack and a second portion located in the gate slit structure. The first portion of the gate slit structure is located over the first isolation structure along the second direction. The first portion of the gate slit structure has a size greater than a size of one of the channel structures in the first direction. In some embodiments, the second portion of the gate slit structure extends through the first isolation structure. The second portion of the gate slit structure has a dimension in the first direction that is greater than a dimension of one of the channel structures. In some embodiments, the first isolation structure is located between two conductive layers of the first stack. In some embodiments, the semiconductor device further includes a second stack of conductive layers and isolation layers extending in the first direction and alternating with each other in the second direction, and a second isolation structure extending in the first direction between the first stack and the second stack. The second stack is adjacent to the first stack in a second direction. In some embodiments, the first isolation structure comprises a dielectric material or a semiconductor material. In some embodiments, the second portion of the gate slit structure includes a plurality of cylinders arranged along a third direction, the third direction being perpendicular to the first direction and the second direction. In some embodiments, the second portion of the gate slit structure further comprises a structure having a surface comprising a series of curves. In some embodiments, the surface of the first