CN-122029952-A - Chip package with multiple HBM stacks

Abstract

Disclosed herein are chip packages that integrate multiple compute die into a memory stack through a single interposer die. The interposer die includes memory controller circuitry that allows multiple compute dies to access the memory stack in an efficient manner.

Inventors

• BRETT P. WILKERSON
• ALAN D. SMITH

Assignees

• 超威半导体公司

Dates

Publication Date

20260512

Application Date

20240625

Priority Date

20240624

Claims (15)

1. 1. A chip package, the chip package comprising: A substrate; An Integrated Circuit (IC) interposer die, the Integrated Circuit (IC) interposer die is mounted on the substrate; a stack of compute dies mounted on the IC interposer die, and A memory stack mounted on the substrate and electrically coupled to the compute die stack through the IC interposer die.
2. 2. The chip package of claim 1, wherein the stack of computing dies further comprises: At least a first computing die and a second computing die.
3. 3. The chip package of claim 2, wherein the first computing die comprises an accelerated computing core and the second computing die comprises a Central Processing Unit (CPU) core.
4. 4. The chip package of claim 2, wherein the first and second compute dies comprise an accelerated compute core.
5. 5. The chip package of claim 1, wherein the stack of computing dies further comprises: A molding compound disposed between the memory stack and the compute die stack, and A metal layer formed in contact with a top surface of the molding compound, a top surface of the memory stack, and a top surface of the compute die stack.
6. 6. The chip package of claim 1, wherein: the substrate is an interposer, and The interposer is mounted on a package substrate.
7. 7. The chip package of claim 2, wherein the IC interposer die further comprises: A memory controller circuit coupled to both the first and second compute die without routing signals through the package substrate, and A cache memory circuit is provided for storing data, the cache memory circuit is coupled to both the first and second compute die, without routing signals through the substrate.
8. 8. A chip package, the chip package comprising: A substrate; a first Integrated Circuit (IC) interposer die mounted on the substrate, the first IC interposer die including a memory controller circuit; a first stack of compute dies mounted on the first IC interposer die, the first stack of compute dies including at least a first compute die and a second compute die, both of the first and second compute dies being communicatively coupled with the memory controller circuit; a first memory stack mounted on the substrate and electrically coupled to the memory controller circuit through the substrate; A cover disposed over the first memory stack and the first compute die stack, and A thermal interface material disposed in contact with both the first stack of computing dies and the cover.
9. 9. The chip package of claim 8, further comprising: a second stack of compute dies mounted on the first IC interposer die, the second stack of compute dies including a plurality of compute dies communicatively coupled with the memory controller circuit.
10. 10. The chip package of claim 8, further comprising: A second memory stack mounted on the substrate and electrically coupled to the memory controller circuit through the substrate.
11. 11. The chip package of claim 8, further comprising: a second IC interposer die mounted on the substrate, the second IC interposer die comprising memory controller circuitry; A second stack of compute dies mounted on the second IC interposer die, the second stack of compute dies including a plurality of compute dies communicatively coupled with the memory controller circuit of the second IC interposer die, and A second memory stack mounted on the substrate and electrically coupled to the memory controller circuit of the second IC interposer die through the substrate.
12. 12. The chip package of claim 2 or 8, wherein at least one or both of the first and second compute dies comprises a Central Processing Unit (CPU) core.
13. 13. The chip package of claim 8, wherein at least one or both of the first and second compute dies comprises an accelerated compute core.
14. 14. The chip package of claim 8, wherein the first stack of computing dies further comprises: A carrier die disposed over the first and second compute die, and A circuit-free dummy die disposed between the first IC interposer die and the carrier die, wherein the dummy die is fusion bonded to at least two of the first computing die, the second computing die, the first IC interposer die, and the carrier die.
15. 15. The chip package of claim 7 or 8, wherein the first IC interposer die further comprises: a cache memory circuit is provided for storing data, the cache memory circuit is coupled to both the first and second compute die, without routing signals through the substrate, Network On Chip (NOC) circuitry; peripheral component interconnect express (PCIe) circuitry; A memory physical layer (PHY) circuit configured to communicate with the first memory stack; a die-to-die PHY configured to communicate with at least one of the first computing die and the second computing die, and An I/O PHY configured to communicate with a device remote from the chip package.

Description

Chip package with multiple HBM stacks Technical Field Embodiments of the present invention relate generally to chip packages having memory stacks, and in particular, to chip packages that interface one or more stacks of computing dies with multiple memory stacks within a single chip package. Background Electronic devices (such as tablet computers, copiers, digital cameras, smart phones, control systems, automated teller machines, data centers, artificial intelligence systems, and machine learning systems, etc.) typically employ electronic and/or photonic components that utilize chip packaging to increase functionality and component density. Conventional chip packaging schemes typically utilize a package substrate that is typically combined with a Through Silicon Via (TSV) interposer substrate and/or other substrates such as fan-out and/or silicon bridging and/or having glass and/or Si and/or organic cores to enable multiple Integrated Circuit (IC) dies to be mounted to a single package substrate. The IC die is mounted to a top surface of the package substrate, and a bottom surface of the package substrate is mounted to a Printed Circuit Board (PCB). In many applications, memory dies are integrated into a chip package to reduce the distance between the memory die and the compute die of the chip package. The shortened distance reduces power consumption and improves device performance. One type of chip package having both a stack of memory dies and at least one connected compute die is known as a High Bandwidth Memory (HBM). The HBM stack typically includes an I/O buffer die on which the memory die is stacked. The I/O buffer die also includes a memory controller. However, in most conventional chip packages having a stack of HBM dies, there are typically compute dies that have complex routing between each compute die and the I/O buffer and memory die having a particular HBM die stack, which typically requires routing through the package substrate. The complex wiring creates scheduling complexity that slows down device performance. In addition, complex routing often requires larger, more expensive interposer and package substrates to accommodate the increased number of routing traces without generating excessive unwanted noise. Larger interposers and package substrates add to manufacturing complexity and cost, and result in slower performance, which is undesirable. Accordingly, there is a need for an improved chip package that interfaces multiple compute dies with a memory stack within a single chip package. Disclosure of Invention Disclosed herein are chip packages that integrate multiple compute die into a memory stack through a single interposer die. The interposer die includes memory controller circuitry that allows multiple compute dies to access the memory stack in an efficient, scalable, robust, and cost-effective manner. In one example, a chip package is provided that includes a substrate, an Integrated Circuit (IC) interposer die, a compute die stack, and a memory stack. The IC interposer die and the memory stack are mounted on the substrate. The stack of compute dies is mounted on the IC interposer die. The mounted memory stack is electrically coupled to the compute die stack through the IC interposer die. In another example, the stack of compute dies further includes at least a first compute die and a second compute die. The first and second computing dies may each include a Central Processing Unit (CPU) core. Alternatively, the first and second computing dies may each include an acceleration computing core. In other examples, one of the first and second computing dies may include a Central Processing Unit (CPU) core, while the other of the first and second computing dies may include an acceleration computing core. In some examples, the stack of compute dies may include a carrier die disposed over one or more compute dies. The carrier die may be free of circuitry, such as without any functional integrated circuits. The carrier die may be fusion bonded to one or more of the compute dies. The fusion bond may utilize an oxide layer. In some examples, the chip package may include a molding compound disposed between the memory stack and the carrier die of the compute die stack. In some examples, a metal layer may be formed in contact with a top surface of the molding compound disposed between the memory stack and the carrier die of the compute die stack, a top surface of the memory stack, and a top surface of the carrier die. In some examples, the chip package may include a lid disposed over the memory stack and the carrier die. A thermal interface material may be disposed in contact with both the metal layer and the cover. The thermal interface material may be a liquid metal or a phase change material. One example of a suitable liquid metal is indium. In some examples, the substrate on which the IC interposer die is mounted is an interposer, and the interposer is mounted on a package substrate. A surface