CN-122029953-A - Semiconductor device and method for manufacturing semiconductor device

CN122029953ACN 122029953 ACN122029953 ACN 122029953ACN-122029953-A

Abstract

A semiconductor device having a miniaturized transistor is provided. The semiconductor device includes a transistor, a first insulating layer, and a second insulating layer. The transistor includes a semiconductor layer, a first conductive layer, and a second conductive layer. The first conductive layer and the first insulating layer are disposed in such a manner that the top surface heights are substantially uniform. The second insulating layer is arranged on the first conductive layer and the first insulating layer. The second conductive layer is disposed on the second insulating layer. The second conductive layer and the second insulating layer are respectively provided with an opening reaching the first conductive layer. The semiconductor layer is provided so as to be in contact with a top surface of the first conductive layer, a side surface of the second insulating layer, and a side surface of the second conductive layer provided in the opening.

Inventors

JINTYOU MASAMI
Toshi Masaka
SATO RAI
YAMADA SHINICHI
IGUCHI YOSHIHIRO
HIZUKA JUNICHI

Assignees

株式会社半导体能源研究所

Dates

Publication Date: 20260512
Application Date: 20241028
Priority Date: 20231102

Claims (15)

1. A semiconductor device, comprising: A transistor; A first insulating layer, and A second insulating layer is provided over the first insulating layer, Wherein the transistor comprises a semiconductor layer, a first conductive layer and a second conductive layer, The first conductive layer is substantially level with the top surface of the first insulating layer, The second insulating layer is disposed on the first conductive layer and the first insulating layer, The second conductive layer is disposed on the second insulating layer, The second conductive layer and the second insulating layer are respectively provided with openings reaching the first conductive layer, In the opening, the semiconductor layer is provided so as to be in contact with the top surface of the first conductive layer, the side surface of the second insulating layer, and the side surface of the second conductive layer.
2. The semiconductor device according to claim 1, Wherein the second insulating layer is provided with a third insulating layer, And the second conductive layer is substantially coincident with the top surface of the third insulating layer.
3. The semiconductor device according to claim 1 or 2, Wherein the transistor comprises a fourth insulating layer, a fifth insulating layer and a third conductive layer, The fourth insulating layer is provided in contact with the top surface of the semiconductor layer and the top surface of the second conductive layer, The third conductive layer is disposed in such a manner as to have a region overlapping the opening and to be in contact with the top surface of the fourth insulating layer, And the fifth insulating layer is disposed on the third conductive layer in such a manner as to fill the opening.
4. The semiconductor device according to claim 1, Wherein the semiconductor layer comprises a metal oxide, The metal oxide comprises two or three selected from indium, element M and zinc, The element M comprises one or more selected from gallium, aluminum, silicon, boron, yttrium, tin, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, cobalt and magnesium, And the second insulating layer comprises silicon oxide or silicon oxynitride.
5. The semiconductor device according to claim 4, Wherein the second insulating layer comprises a sixth insulating layer, a seventh insulating layer on the sixth insulating layer and an eighth insulating layer on the seventh insulating layer, The sixth insulating layer and the eighth insulating layer respectively comprise silicon nitride, silicon oxynitride, hafnium oxide or aluminum oxide, And the seventh insulating layer comprises silicon oxide or silicon oxynitride.
6. A semiconductor device, comprising: A transistor; A first insulating layer, and A second insulating layer is provided over the first insulating layer, Wherein the transistor comprises a semiconductor layer and a first conductive layer, The first conductive layer is substantially level with the top surface of the first insulating layer, The second insulating layer is disposed on the first conductive layer and on the first insulating layer and has an opening to the first conductive layer, The semiconductor layer is provided so as to be in contact with the top surface of the first conductive layer in the opening, the side surface of the second insulating layer in the opening, and the top surface of the second insulating layer.
7. The semiconductor device according to claim 6, Wherein the transistor includes a third insulating layer, a fourth insulating layer, and a second conductive layer, The third insulating layer is disposed in contact with the top surface of the semiconductor layer, The second conductive layer is provided in such a manner as to have a region overlapping with the opening and to be in contact with the top surface of the third insulating layer, And the fourth insulating layer is disposed on the second conductive layer in such a manner as to fill the opening.
8. The semiconductor device according to claim 6, Wherein the semiconductor layer comprises a metal oxide, The metal oxide comprises two or three selected from indium, element M and zinc, The element M comprises one or more selected from gallium, aluminum, silicon, boron, yttrium, tin, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, cobalt and magnesium, And the second insulating layer comprises silicon oxide or silicon oxynitride.
9. The semiconductor device according to claim 8, Wherein the second insulating layer comprises a fifth insulating layer, a sixth insulating layer on the fifth insulating layer and a seventh insulating layer on the sixth insulating layer, The fifth insulating layer and the seventh insulating layer respectively comprise silicon nitride, silicon oxynitride, hafnium oxide or aluminum oxide, The sixth insulating layer includes silicon oxide or silicon oxynitride.
10. A method of manufacturing a semiconductor device, comprising the steps of: forming a first conductive layer and a first insulating layer with the height approximately consistent with the top surface of the first conductive layer; forming a first insulating film on the first conductive layer and the first insulating layer; forming a second conductive layer on the first insulating film so as to have a region overlapping with the first conductive layer; removing a portion of each of the second conductive layer and the first insulating film, thereby forming an opening reaching the first conductive layer and forming a third conductive layer and a second insulating layer, and The semiconductor layer is formed in contact with a side surface of the third conductive layer, a side surface of the second insulating layer, and a top surface of the first conductive layer in the opening, respectively.
11. The method for manufacturing a semiconductor device according to claim 10, Wherein after forming the second conductive layer and before forming the opening, a third insulating layer substantially conforming to a height of a top surface of the second conductive layer is formed on the second conductive layer and on the first insulating film.
12. The method for manufacturing a semiconductor device according to claim 10 or 11, Wherein a fourth insulating layer is formed in contact with the top and side surfaces of the semiconductor layer and the top surface of the third conductive layer after the semiconductor layer is formed, A fourth conductive layer is formed in such a manner as to contact a top surface of the fourth insulating layer and to have a region overlapping the semiconductor layer, Forming a second insulating film on the fourth conductive layer and on the fourth insulating layer in such a manner as to fill the opening, And processing the second insulating film to form a fifth insulating layer with a flat top surface filling the opening.
13. The method for manufacturing a semiconductor device according to claim 10, Wherein a third insulating film and a first photoresist are sequentially formed on the first conductive layer after the first conductive layer is formed, And etching the first photoresist and the third insulating film to form the first insulating layer.
14. The method for manufacturing a semiconductor device according to claim 10 or 13, Wherein a fourth insulating film and a second photoresist are sequentially formed on the second conductive layer and on the first insulating film after the second conductive layer is formed and before the opening is formed, And etching the second photoresist and the fourth insulating film to form a sixth insulating layer having a height substantially equal to a top surface of the second conductive layer.
15. The method for manufacturing a semiconductor device according to claim 10 or 13, Wherein a seventh insulating layer is formed in contact with top and side surfaces of the semiconductor layer and a top surface of the third conductive layer after the semiconductor layer is formed, A fifth conductive layer is formed in contact with the top surface of the seventh insulating layer and has a region overlapping the semiconductor layer, A fifth insulating film and a third photoresist are sequentially formed on the fifth conductive layer and on the seventh insulating layer in such a manner as to fill the opening, And etching the third photoresist and the fifth insulating film to form an eighth insulating layer with a flat top surface filling the opening.

Description

Semiconductor device and method for manufacturing semiconductor device Technical Field One embodiment of the present invention relates to a transistor, a semiconductor device, a display module, and an electronic apparatus. One embodiment of the present invention relates to a method for manufacturing a transistor, a method for manufacturing a semiconductor device, and a method for manufacturing a display device. Note that one embodiment of the present invention is not limited to the above-described technical field. Examples of the technical field of one embodiment of the present invention include a semiconductor device, a display device, a light-emitting device, a power storage device, a lighting device, an input device (for example, a touch sensor), an input/output device (for example, a touch panel), an electronic device on which these devices are mounted, a driving method thereof, and a manufacturing method thereof. Background Semiconductor devices including transistors are widely used in display devices and electronic devices, and high integration and high speed are demanded for the semiconductor devices. For example, in the case of using a semiconductor device for a high-definition display device, a semiconductor device with high integration is required. As one of methods for improving the integration level of transistors, research and development of micro transistors have been conducted. In recent years, there has been a high demand for display devices that can be used for Virtual Reality (VR: virtual Reality), augmented Reality (AR: augmented Reality), alternate Reality (SR: substitutional Reality), or Mixed Reality (MR: mixed Reality). VR, AR, SR, and MR are collectively referred to as XR (Extended Reality). In order to improve the realism and immersion, XR-oriented display devices are required to have high definition and high color reproducibility. Examples of the display device include a liquid crystal display device and a light-emitting device including a light-emitting device (also referred to as a light-emitting element) such as an organic EL (Electro Luminescence: electroluminescence) device or a light-emitting Diode (LED: LIGHT EMITTING Diode). Patent document 1 discloses a VR-oriented display apparatus using an organic EL device (also referred to as an organic EL element). [ Prior Art literature ] [ Patent literature ] [ Patent document 1] International publication No. 2018/087625. Disclosure of Invention Technical problem to be solved by the invention In order to further highly integrate a semiconductor device, it is effective to miniaturize transistors in the semiconductor device and optimize the transistor layout. For example, it is effective to dispose a plurality of transistors in a semiconductor device in a stacked manner in a direction perpendicular to a substrate surface, as compared with disposing the transistors on the same plane. Thus, the semiconductor device can be highly integrated without increasing the area occupied by the transistor in the substrate surface. However, when the transistors are stacked, when the top surface of the underlying transistor has large irregularities, the formed surface of the transistor formed thereon also has irregularities, and it is difficult to form the micro-transistor in a stacked manner. For example, electrodes (a source electrode, a drain electrode, and a gate electrode) in a transistor and wirings connected to the electrodes each have steps with respect to a substrate surface, and stacking the transistor and the wirings causes the steps to be stacked. Therefore, the larger the transistors and wirings provided on the upper layer are, the greater the roughness of the substrate surface is, and the higher the difficulty in manufacturing the structure formed thereon is. Further, when a residue or the like generated during processing remains in a step portion or the like of an electrode or a wiring in a transistor, there is a possibility that the residue is brought into contact with the electrode or the wiring of the transistor stacked on the upper layer, and thus the problem of conduction occurs. Therefore, the surface to be formed of each transistor and wiring is preferably as flat as possible. Accordingly, an object of one embodiment of the present invention is to provide a semiconductor device including a transistor in which irregularities on a top surface are planarized by an insulating layer, and a method for manufacturing the same. Another object of one embodiment of the present invention is to provide a semiconductor device including a micro transistor and a method for manufacturing the same. Another object of one embodiment of the present invention is to provide a small-sized semiconductor device and a method for manufacturing the same. Another object of one embodiment of the present invention is to provide a semiconductor device including a transistor with a large on-state current and a method for manufacturing the same. Another object of