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CN-122029955-A - MOSFET with self-aligned extension

CN122029955ACN 122029955 ACN122029955 ACN 122029955ACN-122029955-A

Abstract

A vertical semiconductor construction element (100) is provided, having a drift region (108), at least one first diode region (109) and a second diode region (109) arranged side by side in the lateral direction, a trench gate (104) arranged laterally between the first diode region (109) and the second diode region (109), wherein the trench gate (104) has a first doping, and an extension region (115) which can be arranged between the trench gate (104) and the drift region (108) and laterally between the trench gate (104) and the first diode region (109) and the second diode region (109), wherein the extension region (115) can be provided as a continuous region.

Inventors

  • S Shi Wei Er
  • H. Bautolf
  • D. Kostkescu
  • W. Fayler
  • A. Martinez limia
  • J-h. alsmeyer

Assignees

  • 罗伯特·博世有限公司

Dates

Publication Date
20260512
Application Date
20240719
Priority Date
20230811

Claims (10)

  1. 1. A vertical semiconductor construction assembly (100) having: A drift region (108), At least one first diode region (109) and a second diode region (109) side by side in the lateral direction; A trench gate (104) arranged laterally between the first diode region (109) and the second diode region (109), wherein the trench gate (104) has a first doping, and An extension region (115) arranged between the trench gate (104) and the drift region (108) and arranged laterally between the trench gate (104) and the first diode region (109) and the second diode region (109), Wherein the expansion area (115) is arranged as a continuous area.
  2. 2. The vertical semiconductor construction element (100) according to claim 1, wherein the extension region (115) is applied such that the extension region (115) is laterally spaced apart from the first diode region (109) and the second diode region (109), respectively.
  3. 3. The vertical semiconductor construction element (100) according to claim 1, wherein the extension region (115) contacts, overlaps or overdopes at least one of the first diode region (109) and the second diode region (109).
  4. 4. A vertical semiconductor construction element (100) according to any one of claims 1 to 3, further having: A source contact (102) arranged on or above at least one of the first diode region (109) and the second diode region (109), wherein the source contact (102) contacts the first diode region (109) and/or the second diode region (109), and A gate dielectric (105) arranged between the trench gate (104) and the semiconductor, at least the extension region (115), and -A drain contact (103), wherein the drift region (108) is arranged on or above the drain contact (103).
  5. 5. A method (400) for producing a vertical semiconductor component (100), the method having: a drift region (108) is constructed, -Structuring (402) at least one first diode region (109) and a second diode region (109) side by side in the lateral direction; Constructing (404) a trench gate (104) located laterally between the first diode region (109) and the second diode region (109), and -Constructing (406) an extension region (115) arranged between the trench gate (104) and the drift region (108) and arranged laterally between the trench gate (104) and the first diode region (109) and the second diode region (109), Wherein the expansion area (115) is arranged as a continuous area.
  6. 6. The method (400) of claim 5, further having: wherein the first diode region (109) and the second diode region (109) are structured by means of a first mask (520), and Wherein the expansion region (115) is constructed by means of a second mask (532), wherein the second mask (532) has a structure consisting of a permeable region and an impermeable region, which is at least partially complementary to the first mask (520).
  7. 7. The method according to claim 6, wherein the method comprises, Wherein the first mask (520) has a permeable area through which the first diode region (109) or the second diode region (109) is configured, and wherein the second mask (532) has at least one permeable area through which the extension region (115) is configured.
  8. 8. The method according to claim 7, Wherein the at least one permeable region of the second mask (532) is structured in such a way that a portion of the impermeable region (530) of the second mask arranged on or above the first mask (520) is removed as the first mask (520) is removed.
  9. 9. The method according to any one of claim 6 to 8, Wherein at least one impermeable region of the second mask (532) is configured in a permeable region of the first mask (520) on or over the first diode region (109) and the second diode region (109).
  10. 10. The method according to claim 9, wherein the method comprises, Wherein the at least one impermeable area of the second mask (532) is configured in a permeable area of the first mask (520) before removing the first mask (520).

Description

MOSFET with self-aligned extension Background Fig. 1 and 2 show schematic cross-sectional views of cells in the active region of a SiC trench gate power MOSFET as a comparative example of a semiconductor construction assembly 1. The semiconductor component 1 has an n+ -doped substrate 6, an n+ -doped buffer layer 7, an n-doped drift region 8,p with a first doping level, an n-doped extension region 10 with a second doping level greater than the first doping level, a p-doped channel region 11, an n+ -doped source region 16, for example a trench gate 4 (also referred to as gate electrode, trench electrode or trench gate electrode) made of polysilicon, a gate oxide 5, a drain metal 3, a source metal 2. One challenge in silicon carbide (SiC) trench gate power MOSFETs is achieving good turn-on characteristics, such as minimum on-resistance (also known as RDS (on) or RDSon) of a low unit area (a) of a field effect transistor, i.e., low RDSon a. For low RDSon a, a high doping is typically required and thus a low resistance of the current carrying layer, in particular of the drift region 8, is required. Another challenge in SiC trench gate power MOSFETs is to keep the blocking voltage as far above the starting voltage as possible. However, for high blocking voltages, a low doping of the drift region 8 is required. Another challenge in SiC trench gate power MOSFETs is to limit the maximum field strength in the oxide of the trench at high blocking voltages for reliability reasons and to achieve as good a short circuit withstand capability as possible. In order to limit the field strength in the gate oxide 5 and a good short-circuit tolerance, a small spacing of the low doping in combination with the diode region 9 to the trench gate 4 and the next diode region 9 is advantageous. One possibility to more advantageously design the trade-off between these opposite requirements is to dope the area between the trench gate 4 and the diode region 9 to a higher degree than the area under the trench gate 4. This region is referred to as the extension 10 (also referred to as the Current extension, english: current SPREADING LAYER). However, the extension 10 has an disadvantageous width. The extension region 10, trench gate 4 and diode region 9 are typically created by a series of photolithography and implantation processes. The pitch of the extension region 10 to the trench gate 4 or the diode region 9 is shifted due to manufacturing-induced fluctuations (see the pitch to the symmetry axis 20 in fig. 1 and 2). In this case, the current flow is unevenly distributed between the two sides of the trench gate 4 in the on condition, and rdson×a increases. To ensure compliance with the specifications taking into account all fluctuations, the advantages of the expansion zone 10 are not fully exploited and the trade-off is not optimal. Disclosure of Invention Advantages of the invention In contrast, the vertical semiconductor component according to the invention with the features according to claim 1 has the advantage that the current flow is (more) uniformly distributed between the two sides of the trench gate in the on-state and thus the proportional RDSon a (more) uniformly distributed between the two sides of the trench gate. Hereby it is achieved that the specifications can be complied with taking into account all process fluctuations. Thereby, the advantages of the extension region can be better utilized and an improved trade-off is achieved. This is achieved by a self-aligned extension region, wherein the extension region is arranged symmetrically (with equidistant spacing) around the trench gate and the spacing between the extension region and the diode region is constant. The semiconductor component can be designed such that RDSon a is particularly low for a given blocking voltage, field strength and short-circuit resistance. This results in a lower cost of the component with a predetermined RDSon x a or a low RDSon x a at a predetermined chip area. Further developments of these aspects and advantageous configurations of the vertical semiconductor component are described in the dependent claims and the description. Drawings Embodiments of the invention are illustrated in the drawings and are explained in more detail below. The drawings show: Fig. 1 is a schematic cross-sectional view of a MOSFET as a comparative example; fig. 2 is a schematic cross-sectional view of a MOSFET as a comparative example; fig. 3 is a schematic cross-sectional view of a semiconductor construction assembly according to various embodiments; FIG. 4 is a flow chart of a method for fabricating a semiconductor construction assembly according to various embodiments, and Fig. 5A to 5G show schematic cross-sectional views of a substrate in a method for producing a semiconductor component. In the following detailed description, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration specific embodim