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CN-122029956-A - Semiconductor wafer having multilayer structure and method for manufacturing the same

CN122029956ACN 122029956 ACN122029956 ACN 122029956ACN-122029956-A

Abstract

A semiconductor wafer having a multilayer structure and a diameter of not less than 150mm and not more than 300mm, wherein the multilayer structure comprises a single crystal silicon substrate having {111} orientation, at least one AlN nucleation layer, an Al z Ga 1‑z N layer, an Al x Ga 1‑x N island and an Al y Ga 1‑y N island, a superlattice structure comprising 20 to 120 periods each consisting of an Al x Ga 1‑x N layer and an Al y Ga 1‑y N layer, and one or more single crystal doped GaN layers having a total thickness of not less than 6 μm, wherein at least one of the one or more single crystal doped GaN layers has a threading dislocation density of not more than 5.0X10 8 cm ‑2 , and wherein 0.3≤z≤0.7, 0.7≤x≤1.0, and 0≤y≤0.5.

Inventors

  • S. Mishler
  • P. Storck
  • THAPA SARAD BAHADUR

Assignees

  • 硅电子股份公司

Dates

Publication Date
20260512
Application Date
20240307
Priority Date
20231012

Claims (15)

  1. 1. A semiconductor wafer having a multilayer structure and a diameter of not less than 150mm and not more than 300mm, wherein the multilayer structure comprises in the following order: a single crystal silicon substrate having {111} orientation; at least one AlN nucleation layer; Al z Ga 1-z N layer; islands of Al x Ga 1-x N and islands of Al y Ga 1-y N; A superlattice structure comprising 20 to 120 periods, each period consisting of a layer of Al x Ga 1-x N and a layer of Al y Ga 1-y N, and One or more single crystal doped GaN layers having a total thickness of not less than 6 μm, Wherein at least one of the one or more single crystal doped GaN layers has a threading dislocation density of no greater than 5.0X10 8 cm -2 , and Wherein z is more than or equal to 0.3 and less than or equal to 0.7, and 0.7 and less than or equal to 0.7 x is less than or equal to 1.0, and y is more than or equal to 0 and less than or equal to 0.5.
  2. 2. The semiconductor wafer of claim 1, wherein 0.80≤x≤1.00 and 0.05≤y≤0.40.
  3. 3. The semiconductor wafer of claim 1 or 2, wherein each period of the superlattice structure has a thickness of no less than 18 nm and no greater than 50: 50 nm.
  4. 4. A semiconductor wafer according to any one of claims 1 to 3, wherein the superlattice structure has an average Al content of less than 50 wt%.
  5. 5. The semiconductor wafer according to any one of claims 1 to 4, wherein a total density of islands of Al x Ga 1-x N and islands of Al y Ga 1-y N is not less than 5.0 x 10 7 cm -2 and not more than 5.0 x 10 9 cm -2 .
  6. 6. The semiconductor wafer of any one of claims 1 to 5, wherein the islands have an aspect ratio of not less than 0.1 and not greater than 10.
  7. 7. The semiconductor wafer of any one of claims 1 to 6, wherein a height of the island is not less than 100 nm and not greater than 1000 nm.
  8. 8. The semiconductor wafer according to any one of claims 1 to 7, wherein a total thickness of layers located between the single crystal silicon substrate and the one or more single crystal doped GaN layers is not less than 0.7 μιη and not more than 1.5 μιη.
  9. 9. The semiconductor wafer of any one of claims 1-8, wherein a total thickness of the at least one AlN nucleation layer is not less than 50nm a and not greater than 500 a nm a.
  10. 10. The semiconductor wafer of any one of claims 1 to 9, wherein the multilayer structure comprises a second superlattice structure between the first superlattice structure and the one or more single crystal doped GaN layers, and the second superlattice structure has a lower average Al content than the superlattice structure defined in claim 1.
  11. 11. A method of manufacturing a semiconductor wafer having a multilayer structure, comprising the following steps in the following order: (i) Providing a monocrystalline silicon substrate having a {111} orientation; (ii) Flowing a gas stream comprising aluminum precursor and no nitrogen precursor through the substrate at a temperature of not less than 700 ℃ and not greater than 900 ℃ such that the total amount of aluminum flowing through the substrate is not less than 0.1 mu mol and not greater than 250 mu mol, (Iii) Depositing a low temperature AlN nucleation layer by flowing a gas stream comprising an aluminum precursor and a nitrogen precursor through the substrate at a temperature of not less than 700 ℃ and not more than 900 ℃, (Iv) Depositing a high temperature AlN nucleation layer by flowing a gas stream comprising an aluminum precursor and a nitrogen precursor through the substrate at a temperature of not less than 950 ℃ and not more than 1100 ℃, (V) Depositing a 0.3≤z≤0.7 Al z Ga 1-z N layer by flowing a gas stream comprising an aluminum precursor, a gallium precursor and a nitrogen precursor through the substrate at a temperature of not less than 950 ℃ and not more than 1050 ℃, (Vi) Alternately depositing 0.7≤x≤1.0 Al x Ga 1-x N and 0≤y≤0.5 Al y Ga 1-y N for 20 to 120 cycles by flowing a gas stream comprising an aluminum precursor, a gallium precursor and a nitrogen precursor through the substrate at a temperature of not less than 950 ℃ and not more than 1100 ℃, wherein the alternation of the deposition is achieved by varying the composition of the gas stream, and (Vii) One or more single crystal doped GaN layers are deposited by flowing a gas stream comprising a gallium precursor, a nitrogen precursor, and a dopant precursor through the substrate at a temperature of not less than 900 ℃ and not greater than 1200 ℃.
  12. 12. The method of manufacturing a semiconductor wafer having a multilayer structure according to claim 11, wherein in each of steps (ii) to (iv), the gas flow satisfies an atomic ratio of a group (V) element generated from the nitrogen precursor to a group (III) element generated from the aluminum precursor of not less than 5 and not more than 100.
  13. 13. A method of manufacturing a semiconductor wafer having a multilayer structure according to claim 11 or 12, wherein the alternation of the deposition in each cycle of step (vi) is achieved by varying the composition of the gas stream such that the atomic ratio of the (V) group element generated from the nitrogen precursor to the (III) group element generated from the aluminum precursor and optionally the gallium precursor in the gas stream alternates between a first value of not more than 100 and a second value of not less than 200.
  14. 14. The method for manufacturing a semiconductor wafer having a multilayer structure according to any one of claims 11 to 13, wherein the method is performed in a reaction chamber having a total pressure of not less than 50 mbar and not more than 300 mbar throughout steps (ii) to (vii).
  15. 15. The method of manufacturing a semiconductor wafer having a multilayer structure according to any one of claims 11 to 14, wherein in step (vi), the growth rate of Al x Ga 1-x N is in the range of 100 to 500 nm/h and the growth rate of Al y Ga 1-y N is in the range of 700 to 1300 nm/h.

Description

Semiconductor wafer having multilayer structure and method for manufacturing the same Technical Field The present invention relates to a semiconductor wafer having a multilayer structure and a method for manufacturing the same. Background In modern electronics, gallium nitride (GaN) power devices are receiving increasing attention for their superior high voltage and high current capability. In particular, vertical GaN power devices are promising candidates for next generation high voltage and high current power switching applications in electric vehicles, smart grids, and renewable energy processes. For such devices, a relatively thin layer of heteroepitaxial GaN film is deposited on a silicon wafer with a buffer layer in between. Due to the lattice mismatch and the mismatch between the coefficients of thermal expansion of Si and GaN, a buffer layer needs to be deposited. Lattice mismatch can result in a relatively high defect density in the GaN layer even if one or more buffer layers are present. In addition, if the GaN layer exceeds a certain thickness, the different thermal expansion coefficients may cause cracks. In order to take account of the different coefficients of thermal expansion, sufficient compressive stress must be added to the GaN layer during growth to counteract the tensile stress it is subjected to during cooling. The relatively high defect density and limited thickness of the GaN layer limit the performance of the power device, for example in terms of its breakdown voltage. Accordingly, there is a need for an improved GaN structure with a new buffer layer that enables the fabrication of GaN drift layers with low defect densities and high thicknesses greater than 5 μm. EP 2727133B 1 discloses a GaN structure with a buffer layer comprising two transition layers of composition B wAlxGayInz N. Thus, a GaN layer having a thickness of more than 5 μm and a relatively low dislocation density can be obtained. However, the buffer layer is relatively thick and complex, and the thickness of the GaN drift layer is limited. Y. Zhang et al J.Phys.D. appl. Phys.51 (2018) 273001 describes a buffer layer capable of producing a GaN layer having a dislocation density of 2x10 8cm-2 and a thickness of less than 6 μm. A. Dadgar et al Phys.stat.Sol. (C) 0, no.6 (2003) describe the reduction of dislocations by a superlattice structure having 15 periods. It is explained that dislocations bend at the interfaces of the superlattice layers, increasing the probability of recombination and annihilation with other dislocations having opposite bergs vectors. The mechanism of dislocation annihilation in this multilayer structure is also discussed by A.E. Romanov and J.S. speck. Appl. Phys. Lett.83.13 (2003): 2569-2571, B. Daudin, B.et al Phys. Rev. B56.12 (1997): R7069, and by M. Imura et al J.Cryst. Growth300.1 (2007): 136-140. Disclosure of Invention The present invention aims to provide a new GaN structure with a GaN drift layer having an increased thickness, a reduced dislocation density and a reduced stress in the GaN drift layer. The above-mentioned problems are solved by a semiconductor wafer having a multilayer structure according to the first aspect of the present invention. In a second aspect, the present invention relates to a method of manufacturing a semiconductor wafer having a multilayer structure. The method is suitable for manufacturing a semiconductor wafer having a multilayer structure according to the first aspect of the present invention. In particular, the inventors have found that certain process conditions can induce the growth of islands of Al xGa1-x N and islands of Al yGa1-y N, where 0.7≤x≤1.0 and 0≤y≤0.5, followed by the formation of a superlattice of these material layers. It has surprisingly been found that the presence of islands reduces dislocations in a relatively small portion of the buffer layer. These islands annihilate dislocations and reduce compressive stress relaxation during GaN growth. Thus, the compressive stress is kept high enough so that the tensile stress during cooling can be compensated. Therefore, a GaN drift layer having a high thickness and a low dislocation density can be obtained in a process susceptible to industrial application. In addition, since dislocations, particularly threading dislocations, can be effectively reduced in a relatively small portion of the buffer layer, the thickness of the buffer layer as a whole can be reduced. This is advantageous because it may reduce manufacturing costs and enhance heat transfer through the buffer layer during operation of the device. The increased compressive stress accumulation compensates for thermal mismatch and enables growth of thick layers of GaN, resulting in crack-free wafers with low residual stress and wafer warpage. This result is critical to achieving thick layers of GaN on silicon substrates. The semiconductor wafer having a multilayer structure according to the first aspect of the present invention has a diam