CN-122029958-A - Semiconductor device with a semiconductor device having a plurality of semiconductor chips

Abstract

The semiconductor device includes a first power line, a second power line, and a third power line formed in a substrate. The semiconductor device includes a first transistor including two semiconductor layers and a first gate electrode formed over a substrate, one of the semiconductor layers being connected to a first power line via a first via hole, and the other of the semiconductor layers being connected to a second power line. The semiconductor device includes a second transistor and a third transistor formed between the first power supply line and the third power supply line and having a second gate electrode. And, the output of the second transistor is electrically connected to the first gate.

Inventors

• Gang Benchun
• Takeno Gi
• WANG WENZHEN

Assignees

• 株式会社索思未来

Dates

Publication Date

20260512

Application Date

20231013

Claims (7)

1. 1. A semiconductor device, comprising: A substrate; A first power line, a second power line, and a third power line formed in the substrate; A first semiconductor layer and a second semiconductor layer formed over the substrate; a third semiconductor layer formed on the first semiconductor layer; A fourth semiconductor layer formed on the second semiconductor layer; a first gate electrode formed between the first semiconductor layer and the second semiconductor layer and between the third semiconductor layer and the fourth semiconductor layer; a first transistor formed between the first power line and the second power line and having the first semiconductor layer, the second semiconductor layer, and the first gate electrode, or having the third semiconductor layer, the fourth semiconductor layer, and the first gate electrode; a fifth semiconductor layer and a sixth semiconductor layer formed on the substrate; A seventh semiconductor layer formed on the fifth semiconductor layer; an eighth semiconductor layer formed on the sixth semiconductor layer; A second gate electrode formed between the fifth and sixth semiconductor layers and between the seventh and eighth semiconductor layers, and A second transistor and a third transistor formed between the first power line and the third power line and having the fifth semiconductor layer, the sixth semiconductor layer, the seventh semiconductor layer, the eighth semiconductor layer, and the second gate electrode, An output of the second transistor is electrically connected to the first gate.
2. 2. The semiconductor device according to claim 1, wherein, The first transistor has the first semiconductor layer, the second semiconductor layer and the first gate electrode, The third semiconductor layer is electrically connected to the fourth semiconductor layer.
3. 3. The semiconductor device according to claim 1, wherein, The first semiconductor layer and the second semiconductor layer have a conductivity type different from a conductivity type of the third semiconductor layer and the fourth semiconductor layer.
4. 4. The semiconductor device according to claim 3, wherein, The semiconductor device includes a plurality of the first transistors, The third semiconductor layers and the fourth semiconductor layers of the plurality of first transistors are electrically connected to each other.
5. 5. The semiconductor device according to claim 1, wherein, The third semiconductor layer and the fourth semiconductor layer are electrically connected to the third power supply line.
6. 6. The semiconductor device according to claim 1, wherein, The semiconductor device includes: A wiring connected to any one of the first semiconductor layer and the second semiconductor layer of the first transistor, and A standard cell having a fourth transistor formed between the second power line and the third power line, The wiring is connected to a source of the fourth transistor.
7. 7. The semiconductor device according to claim 1, wherein, One of the fifth semiconductor layer and the sixth semiconductor layer is integrally formed with the first semiconductor layer, One of the seventh semiconductor layer and the eighth semiconductor layer is integrally formed with the third semiconductor layer.

Description

Semiconductor device with a semiconductor device having a plurality of semiconductor chips Technical Field The present invention relates to a semiconductor device. Background CFET (Complementary field effect Transistor) technology is known, which is formed by stacking transistors. BPR (Buried Power Rail: buried power rail) technology is known, which supplies a power supply potential or a ground potential to a transistor using a buried wiring that forms a conductor in a groove formed on a surface of a semiconductor substrate. A technique of providing a power switching circuit for controlling on/off of supply of a power supply potential in a standard cell or the like is known. Patent document 1 U.S. patent application publication No. 2023/0178435 specification Patent document 2 U.S. patent application publication No. 2023/0067311 specification Patent document 3 U.S. patent application publication No. 2022/0123302 3 specification Patent document 4 U.S. patent application publication No. 2022/0181258 specification Patent document 5 International publication No. 2020/065916 Patent document 6 International publication No. 2020/066797 Patent document 7 International publication No. 2020/217396 Patent document 8 International publication No. 2020/217700 Patent document 9 U.S. patent application publication No. 2021/0366902 specification Patent document 10 U.S. patent application publication No. 2022/0102479 specification Patent document 11 U.S. patent application publication No. 2021/0210600 specification Disclosure of Invention < Problem to be solved by the invention > In the case of connecting the source/drain of the CFET to the wiring of the BPR to form the power switching circuit, how the power switching circuit should be laid out has not been discussed in detail. An object of the present invention is to appropriately layout (layout) a power switching circuit formed using CFET of a wiring whose source/drain is connected to a BPR. < Means for solving the problems > In one aspect of the present invention, a semiconductor device includes a substrate, a first power line, a second power line, and a third power line formed in the substrate, a first semiconductor layer and a second semiconductor layer formed over the substrate, a third semiconductor layer formed over the first semiconductor layer, a fourth semiconductor layer formed over the second semiconductor layer, a first gate formed between the first semiconductor layer and the second semiconductor layer and between the third semiconductor layer and the fourth semiconductor layer, a first transistor formed between the first power line and the second power line and having the first semiconductor layer, the second semiconductor layer, and the first gate, or having the third semiconductor layer, the fourth semiconductor layer, and the first gate, a fifth semiconductor layer and a sixth semiconductor layer formed over the substrate, a seventh semiconductor layer formed over the first semiconductor layer and the second semiconductor layer and between the third semiconductor layer and the fourth semiconductor layer, a first transistor formed between the fifth semiconductor layer and the fifth semiconductor layer, a fifth semiconductor layer and the eighth semiconductor layer, a fifth transistor formed between the fifth semiconductor layer and the eighth semiconductor layer, and the fifth transistor formed between the fifth semiconductor layer and the fifth transistor. < Effect of the invention > According to the technology of the present disclosure, a power switching circuit formed using CFET of a wiring of source/drain connection to a BPR can be appropriately laid out. Drawings Fig. 1 is a plan view showing an example of the layout of a semiconductor device according to the first embodiment. Fig. 2 is a cross-sectional view showing an example of a cross-sectional structure of the semiconductor device of fig. 1. Fig. 3 is a circuit diagram showing an example of a circuit arranged in the standard cell block of fig. 1. Fig. 4 is a perspective view showing an example of the layout of the power switching circuit of fig. 3. Fig. 5 is a perspective view showing an example of a connection method of the top wiring and the wiring of the BPR layer formed on the back surface of the substrate. Fig. 6 is a plan view showing an example of a plan view of the substrate SUB viewed from the top wiring side in the power switching circuit and standard cell of fig. 4. Fig. 7 is a plan view showing an example of a plan view of the power switching circuit and standard cell of fig. 4, the base plate side being viewed from the bottom wiring side. Fig. 8 is a cross-sectional view showing an example of a cross section along the line X1-X1' in fig. 6 and 7. Fig. 9 is a cross-sectional view showing an example of a cross section along the line X2-X2' in fig. 6 and 7. Fig. 10 is a cross-sectional view showing an example of a cross section along the line Y1-Y1' in fig. 6 and 7. Fig. 11 is a plan vie