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CN-122029959-A - Integrated circuit, manufacturing method thereof and electronic equipment

CN122029959ACN 122029959 ACN122029959 ACN 122029959ACN-122029959-A

Abstract

The embodiment of the application discloses an integrated circuit, a preparation method thereof and electronic equipment, and relates to the technical field of semiconductors. An integrated circuit includes a substrate, fins, gate lines, source, drain, isolation layers, power contact structures, and a power distribution network. The substrate has a first surface and a second surface. The fin is located on the first surface. The gate line straddles the fin. The isolation layer is positioned between two adjacent fins and separates the grid line into a plurality of sub grid lines. The power contact structure penetrates the substrate. The power contact structure includes a first power contact and a second power contact. The power distribution network is located on the second surface. The power distribution network is electrically connected to the first power supply contact. The second power contact is electrically connected to the source or the drain. The isolation layer is positioned on two opposite sides of the second power supply contact part along the second direction. The power contact structure is split into the first power contact part and the second power contact part, and the isolation layer is arranged, so that the process difficulty of the integrated circuit is reduced, and the reliability of the integrated circuit is improved.

Inventors

  • ERIC WU
  • ZHU JIFENG

Assignees

  • 华为技术有限公司

Dates

Publication Date
20260512
Application Date
20230928

Claims (13)

  1. An integrated circuit, the integrated circuit comprising: A substrate having first and second opposite surfaces; The device comprises a first surface, a plurality of fins, a plurality of second surface, a plurality of first fins, a plurality of second fins and a plurality of first fins, wherein the fins are positioned on the first surface, extend along a first direction and are arranged at intervals along a second direction, and the first direction and the second direction are parallel to the first surface and are intersected; The grid lines are arranged on the fins in a crossing mode and extend along the second direction; A source and a drain on the fin, one of the source and the drain being a target electrode; The isolating layer is positioned between two adjacent fins and is used for isolating the grid lines into a plurality of sub grid lines; The power supply contact structure penetrates through the substrate, and points to the direction of the first surface along the second surface, and comprises a first power supply contact part and a second power supply contact part positioned on the first power supply contact part, wherein the first power supply contact part is connected with the second power supply contact part; a power distribution network located on the second surface, the power distribution network being electrically connected to the first power contact; Wherein, along the second direction, the isolation layer is located at two opposite sides of the second power contact portion.
  2. The integrated circuit of claim 1, wherein a connection face of the first power contact and the second power contact is located within the first surface.
  3. The integrated circuit of claim 1 or 2, wherein a side surface of the first power contact adjacent to the second power contact is a third surface, and a side surface of the second power contact adjacent to the first power contact is a fourth surface; The orthographic projection of the fourth surface on the first surface is positioned in the orthographic projection range of the third surface on the first surface.
  4. The integrated circuit of any one of claims 1-3, further comprising a gate cutting structure spaced apart from the isolation layer, wherein the gate cutting structure is located between two adjacent sub-gate lines and between two adjacent fins; The grid cutting structure is the same as the isolation layer, and is arranged on the same layer.
  5. The integrated circuit of claim 4, wherein a height of the spacer layer in a direction perpendicular to the first surface is greater than a thickness of the gate cut structure.
  6. The integrated circuit of any one of claims 1-5, further comprising: and the epitaxial contact structure is positioned on the second power supply contact part and the target electrode and is contacted with the second power supply contact part and the target electrode.
  7. The integrated circuit of any one of claims 1-6, further comprising a first dielectric layer; The first dielectric layer is positioned between the second surface and the power distribution network and between the first power supply contact and the substrate; The first power supply contact part is far away from one side surface of the second power supply contact part and is flush with one side surface of the first dielectric layer far away from the second surface.
  8. A method of manufacturing an integrated circuit, the method comprising: The method comprises the steps of forming an initial integrated circuit, wherein the initial integrated circuit comprises a substrate, a plurality of fins, a second dielectric layer and a sacrificial layer, the substrate is provided with a first surface and a second surface which are opposite to each other, the fins are positioned on the first surface and extend along a first direction and are arranged at intervals along a second direction, the second dielectric layer is filled between two adjacent fins and covers the fins, the sacrificial layer is positioned on the second dielectric layer and comprises a sacrificial gate which is arranged on the fins in a crossing mode, the sacrificial gate extends along the second direction, and the first direction and the second direction are parallel to the first surface and are intersected; forming a first gate cutting groove in the sacrificial layer, wherein the first gate cutting groove is positioned between two adjacent fins and cuts off the sacrificial gate; forming an isolation layer, wherein the isolation layer at least covers the side wall of the first gate cutting groove; Forming a second power supply contact in the first gate cutting groove; Forming a first power supply contact part on one side of the second power supply contact part, which is close to the second surface, wherein the first power supply contact part is connected with the second power supply contact part; And forming a power distribution network on the second surface, wherein the power distribution network is electrically connected with the first power supply contact part.
  9. The method of claim 8, wherein during the forming of the first gate cut trench in the sacrificial layer, a second gate cut trench is also formed; the second grid cutting groove is positioned between two adjacent fins and cuts off the sacrificial grid, and the depth of the second grid cutting groove is smaller than that of the first grid cutting groove along the direction perpendicular to the first surface; And in the process of forming the isolation layer, a grid cutting structure is also formed, and the grid cutting structure is positioned in the second grid cutting groove.
  10. The manufacturing method according to claim 8 or 9, wherein the forming of the first power supply contact portion on the side of the second power supply contact portion near the second surface includes: Etching the substrate from the side of the second surface to form a contact groove, wherein the contact groove exposes one side surface of the second power supply contact part close to the second surface; the first power contact is formed within the contact trench.
  11. The method of manufacturing of claim 10, wherein the isolation layer also covers a bottom wall of the first gate cut trench; The method of manufacturing further comprises, prior to forming the first power contact within the contact trench: and removing a part of the isolation layer covering the bottom wall of the first gate cutting groove through the contact groove, and exposing one side surface of the second power supply contact part close to the second surface.
  12. The method according to any one of claims 8 to 11, wherein before the forming of the power distribution network on the second surface, the method further comprises: Removing the sacrificial gate to form a gate line groove; And filling conductive materials in the grid line groove to form a grid line.
  13. An electronic device, the electronic device comprising: A circuit board, and a plurality of circuit boards, The integrated circuit of any one of claims 1-7, connected to the circuit board.

Description

Integrated circuit, manufacturing method thereof and electronic equipment Technical Field The present application relates to the field of semiconductor technologies, and in particular, to an integrated circuit, a method for manufacturing the integrated circuit, and an electronic device. Background With the continuous shrinking of semiconductor devices, the density of transistors in a chip is higher and higher, and the shrinking pressure faced by metal interconnections is also higher and higher. The back side power supply network (backside power delivery network, BSPDN) technology transfers wires for power supply (including power supply, ground and other components) from the front side of the chip to the back side of the chip, so that the chip area micro-gain can be realized, the current resistance voltage drop (IR drop) can be improved, the chip performance is improved, and the power consumption is reduced. In order to optimize the power supply capability, it is currently proposed to move the power supply rail into the substrate, forming a buried power supply rail (buried power rail, BPR). In this scheme a power contact/power tree is provided for connecting the transistors in the chip to the back side supply network. The formation process required for the power contact structure is very difficult. In addition, due to the arrangement of the embedded power rail and other structures, the space between the power contact structure and the existing structure (such as a grid line, a fin and the like) in the chip is compressed, so that the process difficulty of the power contact structure is further increased, and reliability risks are brought. Disclosure of Invention The embodiment of the application provides an integrated circuit, a preparation method thereof and electronic equipment, which are used for reducing the process difficulty of the integrated circuit and improving the reliability of the integrated circuit. In order to achieve the above purpose, the embodiment of the present application adopts the following technical scheme: In a first aspect, an integrated circuit is provided that includes a substrate, a plurality of fins, a gate line, a source, a drain, an isolation layer, a power contact structure, and a power distribution network. The substrate has first and second surfaces that are opposite. A plurality of fins is located on the first surface. The fins extend along the first direction and are arranged at intervals along the second direction. The first direction and the second direction are both parallel to the first surface and intersect. The grid lines are arranged across the fins. The gate line extends along the second direction. The isolation layer is positioned between two adjacent fins. The isolation layer partitions the gate line into a plurality of sub-gate lines. A source and a drain are located on the fin, one of the source and the drain being a target electrode. The power contact structure penetrates the substrate. The power contact structure comprises a first power contact part and a second power contact part positioned on the first power contact part along the direction that the second surface points to the first surface. The first power contact portion is connected with the second power contact portion. The second power supply contact is electrically connected to the target electrode. The power distribution network is located on the second surface. The power distribution network is electrically connected to the first power supply contact. The isolation layer is positioned on two opposite sides of the second power supply contact part along the second direction. The integrated circuit provided by some embodiments of the present application may have the first power contact portion and the second power contact portion prepared independently of each other by providing the power contact structure as the first power contact portion and the second power contact portion connected to each other, so that the trench for accommodating the power contact structure is formed in two steps, wherein one step may form the trench for accommodating the first power contact portion and the other step may form the trench for accommodating the second power contact portion. Because the aspect ratio of the first power contact portion and the aspect ratio of the second power contact portion are smaller, compared with the power contact structure formed through the substrate by one-time preparation, the difficulty of the etching process and the metal filling process required for preparing the first power contact portion is lower, and the difficulty of the etching process and the metal filling process required for preparing the second power contact portion is lower. Thus, the difficulty of the process for forming the power contact structure in the embodiment of the application can be reduced. In addition, the embodiment of the application can reduce the precision requirements of the processes such as alignment, photoe