Search

CN-122029960-A - Semiconductor device with a semiconductor device having a plurality of semiconductor chips

CN122029960ACN 122029960 ACN122029960 ACN 122029960ACN-122029960-A

Abstract

The semiconductor device includes a first power line, a second power line, and a third power line formed on a substrate, a first semiconductor layer and a second semiconductor layer formed over the substrate, and a third semiconductor layer and a fourth semiconductor layer formed on the first semiconductor layer and the second semiconductor layer, respectively. Further, the semiconductor device includes a first gate electrode formed between the first semiconductor layer and the second semiconductor layer and between the third semiconductor layer and the fourth semiconductor layer, and a switching transistor formed between the first power line and the second power line, the switching transistor having the first semiconductor layer and the second semiconductor layer and the first gate electrode, or having the third semiconductor layer and the fourth semiconductor layer and the first gate electrode.

Inventors

  • Gang Benchun
  • Takeno Gi
  • WANG WENZHEN

Assignees

  • 株式会社索思未来

Dates

Publication Date
20260512
Application Date
20231013

Claims (8)

  1. 1. A semiconductor device, comprising: A substrate; A first power line, a second power line, and a third power line formed in the substrate; A first semiconductor layer and a second semiconductor layer formed over the substrate; a third semiconductor layer formed on the first semiconductor layer; A fourth semiconductor layer formed on the second semiconductor layer; a first gate formed between the first semiconductor layer and the second semiconductor layer and between the third semiconductor layer and the fourth semiconductor layer, and And a switching transistor formed between the first power line and the second power line, having the first semiconductor layer, the second semiconductor layer, and the first gate electrode, or having the third semiconductor layer, the fourth semiconductor layer, and the first gate electrode.
  2. 2. The semiconductor device according to claim 1, wherein, The switching transistor has the first semiconductor layer, the second semiconductor layer and the first gate electrode, The third semiconductor layer is electrically connected to the fourth semiconductor layer.
  3. 3. The semiconductor device according to claim 1, wherein, The first semiconductor layer and the second semiconductor layer have a conductivity type different from a conductivity type of the third semiconductor layer and the fourth semiconductor layer.
  4. 4. The semiconductor device according to claim 3, wherein, The semiconductor device includes a plurality of the switching transistors; the third semiconductor layer and the fourth semiconductor layer of the plurality of switching transistors are electrically connected to each other.
  5. 5. The semiconductor device according to claim 4, wherein, The semiconductor device includes: A first wiring interconnecting a plurality of the third semiconductor layers adjacent in a second direction different from a first direction in which the first power supply line, the second power supply line, and the third power supply line extend; A second wiring interconnecting the plurality of fourth semiconductor layers adjacent in the second direction, and And a third wiring which extends in the first direction at an upper layer of the first wiring and the second wiring and interconnects the first wiring and the second wiring.
  6. 6. The semiconductor device according to claim 1, wherein, The third semiconductor layer and the fourth semiconductor layer are electrically connected to the second power supply line.
  7. 7. The semiconductor device according to claim 1, wherein, A fourth wiring connected to any one of the first semiconductor layer and the second semiconductor layer of the switching transistor, and A standard cell having a PMOS transistor formed between the second power supply line and the third power supply line, The fourth wiring is connected to a source of the PMOS transistor.
  8. 8. The semiconductor device according to claim 1, wherein, The first semiconductor layer and the second semiconductor layer have the same conductivity type as the third semiconductor layer and the fourth semiconductor layer.

Description

Semiconductor device with a semiconductor device having a plurality of semiconductor chips Technical Field The present invention relates to a semiconductor device. Background CFET (Complementary field effect Transistor) technology is known, which is formed by stacking transistors. BPR (Buried Power Rail: buried power rail) technology is known, which supplies a power supply potential or a ground potential to a transistor using a buried wiring that forms a conductor in a groove formed on a surface of a semiconductor substrate. A technique of providing a power switching circuit for controlling on/off of supply of a power supply potential in a standard cell or the like is known. Patent document 1 U.S. patent application publication No. 2023/0178435 specification Patent document 2 U.S. patent application publication No. 2023/0067311 specification Patent document 3 U.S. patent application publication No. 2022/0123302 3 specification Patent document 4 U.S. patent application publication No. 2022/0181258 specification Patent document 5 International publication No. 2020/065916 Patent document 6 International publication No. 2020/066797 Patent document 7 International publication No. 2020/217396 Patent document 8 International publication No. 2020/217700 Patent document 9 U.S. patent application publication No. 2021/0366902 specification Patent document 10 U.S. patent application publication No. 2022/0102479 specification Patent document 11 U.S. patent application publication No. 2021/0210600 specification Disclosure of Invention < Problem to be solved by the invention > In the case of connecting the source/drain of the CFET to the wiring of the BPR to form the power switching circuit, how the power switching circuit should be laid out has not been discussed in detail. An object of the present invention is to appropriately layout (layout) a power switching circuit formed using CFET of a wiring whose source/drain is connected to a BPR. < Means for solving the problems > In one aspect of the present invention, a semiconductor device includes a substrate, first, second, and third power lines formed in the substrate, first and second semiconductor layers formed over the substrate, a third semiconductor layer formed on the first semiconductor layer, a fourth semiconductor layer formed on the second semiconductor layer, a first gate formed between the first and second semiconductor layers and between the third and fourth semiconductor layers, and a switching transistor formed between the first and second power lines, having the first, second, and first gates, or having the third, fourth, and first semiconductor layers. < Effect of the invention > According to the technology of the present disclosure, a power switching circuit formed using CFET of a wiring of source/drain connection to a BPR can be appropriately laid out. Drawings Fig. 1 is a plan view showing an example of the layout of a semiconductor device according to the first embodiment. Fig. 2 is a cross-sectional view showing an example of a cross-sectional structure of the semiconductor device of fig. 1. Fig. 3 is a circuit diagram showing an example of a circuit arranged in the standard cell block of fig. 1. Fig. 4 is a circuit diagram illustrating an example of the power switch circuit of fig. 3. Fig. 5 is a perspective view showing an example of the layout of the power switching circuit and the standard cell of fig. 3. Fig. 6 is a perspective view showing an example of a connection method between a top wiring and a wiring of a BPR layer formed on a substrate. Fig. 7 is a plan view showing an example of a plan view of the substrate SUB viewed from the top wiring side in the power switching circuit and standard cell of fig. 5. Fig. 8 is a plan view showing an example of a plan view of the power switching circuit and the standard cell of fig. 5, the substrate side being viewed from the bottom wiring side. Fig. 9 is a cross-sectional view showing an example of a cross section along the line X1-X1' in fig. 7 and 8. Fig. 10 is a cross-sectional view showing an example of a cross section along the line X2-X2' in fig. 7 and 8. Fig. 11 is a cross-sectional view showing an example of a cross section along the line Y1-Y1' in fig. 7 and 8. Fig. 12 is a perspective view showing an example of the layout of the power switching circuit and the standard cell in the second embodiment. Fig. 13 is a circuit diagram showing an example of a power switching circuit and a standard cell in the third embodiment. Fig. 14 is a perspective view showing an example of the layout of the power switching circuit and the standard cell of fig. 13. Fig. 15 is a plan view showing an example of a plan view of the substrate SUB viewed from the top wiring side in the power switching circuit and standard cell of fig. 14. Fig. 16 is a plan view showing an example of a plan view of the power switching circuit and standard cell of fig. 14, the base plate side being viewed from the bottom wiring side. Fig