CN-122029983-A - Substrate processing method, semiconductor device manufacturing method, hard mask forming method, substrate processing apparatus, and program

Abstract

The method comprises a step of preparing a substrate by exposing the substrate to a source gas, a step of forming a multilayer film of a predetermined thickness having a controlled grain size on the substrate by performing a cycle including a step of depositing a first film by exposing the substrate to the source gas and a step of exposing the substrate to a crystal growth inhibiting gas or a predetermined gas for forming a second film having a different quality from the first film, and a step of performing ion implantation using the patterned multilayer film as a hard mask.

Inventors

• PU TIANYAN
• KUDO TOSHIO
• ITATANI HIDEHARU

Assignees

• 株式会社国际电气

Dates

Publication Date

20260512

Application Date

20240924

Priority Date

20240313

Claims (20)

1. 1. A substrate processing method is characterized by comprising: (a) A step of preparing a substrate by performing a cycle including a step of depositing a first film by exposing the substrate to a source gas and a step of exposing the substrate to a crystal growth inhibiting gas or a predetermined gas for forming a second film having a different film quality from the first film, a step of forming a multilayer film of a predetermined thickness having a controlled grain size on the substrate by performing a cycle a predetermined number of times, and patterning the multilayer film, and (B) And performing ion implantation using the patterned multilayer film as a hard mask.
2. 2. The method for processing a substrate according to claim 1, wherein, The predetermined number of times is set so that the average grain size of the crystals of the multilayer film becomes equal to or smaller than a predetermined value.
3. 3. The method for processing a substrate according to claim 1, wherein, The predetermined number of times is set so that an absolute value or a gradient of residual stress of the multilayer film in a state where the multilayer film is exposed on the surface of the substrate becomes a predetermined value or less.
4. 4. The substrate processing method according to claim 1, further comprising: (c) And (b) annealing the multilayer film before the step (b).
5. 5. The method for processing a substrate according to claim 1, wherein, The first film is a polycrystalline film mainly composed of silicon and/or germanium, The grains of the two first films separated by the exposing step are independent.
6. 6. The method for processing a substrate according to claim 1, wherein, The plurality of first films formed according to the predetermined number of times have substantially equal average particle diameters.
7. 7. The method for processing a substrate according to claim 1, wherein, The first film is a polycrystalline or amorphous film having an average particle diameter of 0.2 μm or less.
8. 8. The method for processing a substrate according to claim 1, wherein, The substrate is a SiC substrate.
9. 9. The method for processing a substrate according to claim 1, wherein, The first film is a polycrystalline or amorphous film having an average particle diameter of 0.2 μm or less.
10. 10. The method for processing a substrate according to claim 1, wherein, The predetermined thickness is 1-20 [ mu ] m, and is set in such a manner that the multilayer film has a blocking energy corresponding to a mask for ion implantation of 1-20 MeV.
11. 11. The method for processing a substrate according to claim 1, wherein, The absolute value of the residual stress of the multilayer film is 100MPa or less.
12. 12. The method for processing a substrate according to claim 1, wherein, The multilayer film has a surface roughness Ra of 15nm or less.
13. 13. The method for processing a substrate according to claim 1, wherein, (A) The substrate prepared in (a) has a buffer layer under the multilayer film.
14. 14. The substrate processing method according to claim 1, further comprising: (d) A step of removing the multilayer film after (b), and (E) And (d) annealing the substrate to activate the impurity implanted in (c).
15. 15. The method for processing a substrate according to claim 1, wherein, The step (b) inverts the conductivity by the ion implantation, and forms a well having a depth of 3 μm or more in the SiC film.
16. 16. A method for manufacturing a semiconductor device is characterized by comprising: (a) A step of preparing a substrate by performing a cycle including a step of depositing a first film by exposing the substrate to a source gas and a step of exposing the substrate to a crystal growth inhibiting gas or a predetermined gas for forming a second film having a different film quality from the first film, a step of forming a multilayer film of a predetermined thickness having a controlled grain size on the substrate by performing a cycle a predetermined number of times, and patterning the multilayer film, and (B) And performing ion implantation using the patterned multilayer film as a hard mask.
17. 17. A hard mask for ion implantation is characterized in that, A multilayer film having a predetermined thickness, in which a crystal grain size is controlled by a predetermined number of cycles including a step of depositing a first film by exposing a substrate to a source gas and a step of exposing the substrate to a crystal growth inhibition gas or a predetermined gas for forming a second film having a different film quality from the first film, is used as a hard mask for ion implantation.
18. 18. A method for forming a hard mask for ion implantation is characterized by comprising: A step of forming a multilayer film having a thickness of 1 [ mu ] m to 20 [ mu ] m on a substrate by performing a cycle including (a) a step of depositing a first film of polycrystalline or amorphous by exposing a substrate made of SiC or GaN to a source gas and (b) a step of exposing the substrate to a crystal growth inhibition gas or a predetermined gas for forming a second film having a different quality from the first film, The grains of the two first films separated by step (b) are independent.
19. 19. A substrate processing apparatus is characterized by comprising: A processing chamber, and A control unit configured to be capable of performing control by performing a cycle including (a) a step of depositing a first film of polycrystalline or amorphous material by exposing a substrate made of SiC or GaN to a source gas in the processing chamber, and (b) a step of exposing the substrate to a predetermined gas of a crystal growth inhibition gas or a second film of a different film quality from the first film, as a hard mask for ion implantation, on the substrate by performing the cycle a predetermined number of times, The grains of the two first films separated by step (b) are independent.
20. 20. A program, characterized in that, A step of causing a substrate processing apparatus to execute, by a computer, a step of forming a multilayer film having a thickness of 1 μm to 20 μm as a hard mask for ion implantation on a substrate by performing a cycle including (a) a step of depositing a first film of polycrystalline or amorphous by exposing a SiC or GaN substrate to a source gas in the processing chamber, and (b) a step of exposing the substrate to a crystal growth inhibition gas or a predetermined gas for forming a second film having a different film quality from the first film, in a processing chamber of the substrate processing apparatus, The grains of the two first films separated by step (b) are independent.

Description

Substrate processing method, semiconductor device manufacturing method, hard mask forming method, substrate processing apparatus, and program Technical Field The invention relates to a substrate processing method, a semiconductor device manufacturing method, a hard mask forming method, a substrate processing apparatus, and a program. Background As a step of manufacturing a semiconductor device, a process of forming a polycrystalline film on a substrate may be performed (for example, see patent documents 1 to 8). As another step, a process of performing ion implantation using a silicon film or the like formed on a substrate as a hard mask may be performed (for example, see patent document 9). Prior art literature Patent literature Patent document 1 Japanese patent laid-open No. 2020-43262 Patent document 2 Japanese patent application laid-open No. 2016-1760 Patent document 3 Japanese patent application laid-open No. 2009-81457 Patent document 4 Japanese patent application laid-open No. 2013-197307 Patent document 5 Japanese patent laid-open No. 2009-147388 Patent document 6 Japanese patent application laid-open No. 2018-160516 Patent document 7 International publication No. 2022/064578 Patent document 8 International publication No. 2024/024366 Patent document 9 International publication No. 2015/060069 Disclosure of Invention Problems to be solved by the invention The deeper it is desirable to implant impurities into the substrate with high energy, the greater the thickness of the mask is required. In addition, in order to prevent the occurrence of unrecoverable crystal damage, an SiC (silicon carbide) substrate is ion-implanted at a high temperature. In this case, it may be difficult to maintain the quality required for the mask at low cost. The present invention provides a technique for a mask that can be used for high energy ion implantation. Solution for solving the problem According to one aspect of the present invention, there is provided a technique including: (a) A step of preparing a substrate by performing a cycle including a step of depositing a first film by exposing the substrate to a source gas and a step of exposing the substrate to a crystal growth inhibiting gas or a predetermined gas for forming a second film having a different film quality from the first film, a step of forming a multilayer film of a predetermined thickness having a controlled grain size on the substrate by performing a cycle a predetermined number of times, and patterning the multilayer film, and (B) And performing ion implantation using the patterned multilayer film as a hard mask. ADVANTAGEOUS EFFECTS OF INVENTION According to the present invention, a mask can be utilized in high-energy ion implantation. Drawings Fig. 1 is a cross-sectional view of a SiC superjunction MOSFET (metal oxide semiconductor field effect transistor) according to one embodiment. Fig. 2 is a flowchart of a method of manufacturing a SiC superjunction MOSFET according to an embodiment. Fig. 3A is a cross-sectional view of a substrate during a process of a method of manufacturing an embodiment. Fig. 3B is a cross-sectional view of a substrate during a process of a fabrication method of an embodiment. Fig. 3C is a cross-sectional view of a substrate during a process of a method of manufacturing in one embodiment. Fig. 3D is a cross-sectional view of a substrate during a process of a method of fabrication of an embodiment. Fig. 4 is a block diagram of a substrate processing apparatus that performs a polysilicon layer formation process in a manufacturing method according to one embodiment. Fig. 5 is a functional block diagram of a control unit of the substrate processing apparatus according to the embodiment. Fig. 6 is a diagram showing a sequence of a polysilicon layer forming process according to one embodiment. Fig. 7A is a cross-sectional TEM (transmission electron microscope) image of a polysilicon layer formed as a multilayer film. Fig. 7B is a cross-sectional TEM image of a single polysilicon layer formed by the substrate processing step of the comparative example. Fig. 8 is a graph showing measurement results of residual stress of a film formed on a substrate in the absence of an annealing step and in the presence of an annealing step in a substrate processing step according to one embodiment. Fig. 9 is a depth profile of impurity concentration after ion implantation using the polysilicon layer of one embodiment and the comparative example as a mask. Detailed Description Hereinafter, an example of a Super junction (Super junction) structure in which a SiC power MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) is formed by ion implantation in one embodiment of the present invention will be described with reference to the drawings. The drawings used in the following description are schematic drawings, and dimensional relationships of elements shown in the drawings, ratios of the elements, and the like are not necessarily the same as t