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CN-122029988-A - Method for polishing silicon wafer

CN122029988ACN 122029988 ACN122029988 ACN 122029988ACN-122029988-A

Abstract

Provided is a silicon wafer polishing method capable of producing a silicon wafer having a small PID number. A silicon wafer polishing method comprises an F/T value calculation step (S11) for measuring a load current value F of a motor for rotationally driving a rotary table and a surface temperature T of a polishing pad in a silicon wafer polishing step, a PID evaluation step (S12) for observing the surface of a silicon wafer after the silicon wafer polishing step and counting the number of PIDs (Polishing Induced Defect, defects caused by polishing), and a polishing condition adjustment step (S13) for determining polishing conditions under which the number of PIDs of the silicon wafer becomes a target F/T value equal to or smaller than a threshold value, with reference to data on the F/T value and the PID number prepared in advance. The polishing conditions obtained in the polishing condition adjustment step (S13) are applied to the polishing steps of the next batch and thereafter.

Inventors

  • Nishiura kazuyoshi
  • TAKADA KOSUKE

Assignees

  • 胜高股份有限公司

Dates

Publication Date
20260512
Application Date
20241001
Priority Date
20231024

Claims (9)

  1. 1. A polishing method for a silicon wafer, wherein a silicon wafer held by a polishing head is pressed against a polishing pad attached to a rotary table, and the polishing pad and the rotary table are rotated while slurry is supplied to the surface of the polishing pad, thereby polishing one surface of the silicon wafer, The device is provided with: an F/T value calculation step of measuring a load current value F of a motor for rotationally driving the rotary table and a surface temperature T of the polishing pad in a polishing step of a silicon wafer, and calculating an F/T value; A PID evaluation step of observing the surface of the silicon wafer after the polishing step of the silicon wafer, counting the number of PID (Polishing Induced Defect, polishing-induced defects), and A polishing condition adjustment step of determining polishing conditions for obtaining a target F/T value in which the PID number of the silicon wafer is equal to or less than a threshold value, with reference to data on the F/T value and PID number prepared in advance; the polishing conditions obtained in the polishing condition adjustment step are applied to the polishing step of the next batch or later.
  2. 2. The method for polishing a silicon wafer according to claim 1, wherein, The device is provided with: A1 st polishing step of polishing the 1 st silicon wafer, and A 2 nd polishing step of polishing a 2 nd silicon wafer different from the 1 st silicon wafer by using the same wafer polishing apparatus as that used in the 1 st polishing step; the F/T value calculating step calculates an F/T value in the 1 st polishing step; The PID evaluation step counts the number of PIDs by observing the surface of the 1 st silicon wafer after the 1 st polishing step; the polishing condition adjustment step refers to the related data and determines a polishing condition that results in a target F/T value where the PID number of the 1 st silicon wafer is equal to or less than the threshold value; The 2 nd polishing step polishes the 2 nd silicon wafer under the polishing conditions obtained in the polishing condition adjustment step.
  3. 3. A polishing method for a silicon wafer according to claim 2, wherein, The 2 nd polishing step adjusts the F/T value by adjusting at least one of a rotation speed of the rotary platen and a pressurizing pressure of the polishing head.
  4. 4. A polishing method for a silicon wafer according to claim 2, wherein, When the F/T value obtained in the 1 st polishing step is smaller than the target F/T value, the 2 nd polishing step increases the F/T value by making the rotation speed of the rotation table in the 2 nd polishing step smaller than the rotation speed of the rotation table in the 1 st polishing step or making the pressurizing pressure of the polishing head in the 1 st polishing step larger than the pressurizing pressure of the polishing head in the 2 nd polishing step.
  5. 5. A polishing method for a silicon wafer according to claim 2, wherein, The 2 nd polishing step is performed under polishing conditions in which the F/T value is 0.2 (A/° C) to 0.6 (A/° C), and the 2 nd silicon wafer is polished.
  6. 6. A polishing method for a silicon wafer according to claim 2, wherein, The F/T value calculating step calculates the F/T value using data acquired during a predetermined period immediately before the end of the 1 st polishing step.
  7. 7. The method for polishing a silicon wafer according to claim 1, wherein, The threshold value of the PID number is 30 or less.
  8. 8. The method for polishing a silicon wafer according to claim 7, The diameter of the silicon wafer was 300mm.
  9. 9. The method for polishing a silicon wafer according to claim 1, wherein, The device comprises: a rough polishing step of rough polishing the silicon wafer, and A finish polishing step of performing finish polishing of the silicon wafer after the rough polishing step; The F/T value calculation step, the PID evaluation step, and the polishing condition adjustment step are performed in the finish polishing step.

Description

Method for polishing silicon wafer Technical Field The present invention relates to a polishing method for a silicon wafer. Background Silicon wafers are widely used as substrate materials for semiconductor devices. The silicon wafer is produced by sequentially performing the steps of slicing, chamfering, polishing, etching, double-sided polishing, single-sided polishing, cleaning, and the like on a single crystal silicon ingot. Among them, the single-sided Polishing step is a step required for improving flatness by removing irregularities and undulations on the wafer surface, and is a mirror surface processing by a CMP (CHEMICAL MECHANICAL Polishing) method. In general, a single wafer polishing apparatus (CMP apparatus) is used for single-sided polishing of a silicon wafer. The wafer polishing apparatus includes a rotary table to which a polishing cloth is attached, and a polishing head which holds a wafer on the rotary table while pressing the wafer, and one surface of the wafer is polished by rotating the rotary table and the polishing head while supplying slurry. Regarding the wafer polishing technique, for example, patent document 1 describes that in order to obtain a single crystal silicon wafer having a small PID (Polishing Induced Defect, defect due to polishing), in a finish polishing step which is the final stage of a multi-stage polishing step in which a wafer is polished by sandwiching a polishing slurry between the wafer and a polishing cloth, a polishing rate is set to be more than 10nm/min, a polishing rate at the end point is set to be 5nm/min or less, and a polishing margin in the finish polishing is set to be 5nm or more. Patent document 2 describes that HEC (hydroxyethyl cellulose) is used as a CMP slurry used for CMP finishing of a silicon wafer, and that the slurry is filtered immediately before chemical mechanical polishing by a CMP apparatus. The number of PID generated can be reduced by removing aggregates, impurities, and the like existing in the polishing composition by using a filter. Prior art literature Patent literature Patent document 1 Japanese patent application No. 4696086 Patent document 2 Japanese patent application laid-open No. 2021-095431. Disclosure of Invention Problems to be solved by the invention As described above, in the polishing process of the silicon wafer, the generation of PID becomes a problem. PID is a linear convex defect of about 100nm in length, which is introduced into a wafer in the polishing step, and causes device defects. Since particles and impurities having a larger amount than PID are adhered to the surface of the silicon wafer, the existence of PID is not so conspicuous. However, particles and the like are removed due to the improvement of the cleaning technology in recent years, and the existence of PID becomes remarkable. In recent years, silicon wafers are strongly demanded to have as few PIDs as possible. It is conceivable that PID is formed from the residue of slurry used in the grinding process. During polishing, aggregates of undissolved components of water-soluble polymers (HEC) in the CMP slurry are integrated with abrasive grains and other foreign matters and coarsened, thereby adsorbing the aggregates on the surface of the silicon wafer. Further, it is conceivable that a convex defect is formed due to a difference in etching rate between the adsorbed portion of the aggregate and the surrounding area. As described above, the number of PID generated can be reduced by removing aggregates and impurities in the slurry by using a filter or the like, but further improvement is demanded. Accordingly, an object of the present invention is to provide a silicon wafer having a small PID number and a silicon wafer polishing method capable of producing the silicon wafer. Means for solving the problems The present inventors have conducted intensive studies and as a result, have found that the F/T value measured in the polishing step of a silicon wafer has a certain correlation with the number of PIDs generated in the silicon wafer, and that the PID can be reduced by controlling the F/T value. The F/T value is the ratio of the mechanical action to the chemical action of CMP, and by increasing the F/T value, the mechanical action becomes large. The aggregates of undissolved components of HEC, which are the cause of PID, tend to remain under polishing conditions where the contribution of chemical action such as etching is large, but are easily removed under polishing conditions where the contribution of mechanical action is large. Therefore, by performing the evaluation using the F/T value, the polishing conditions can be determined more accurately than the evaluation using the machining allowance and the polishing rate. The present invention is based on the technical knowledge, and is characterized by comprising an F/T value calculation step of measuring a load current value F of a motor for rotationally driving the rotary platen and a surface tempe