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CN-122030002-A - Power semiconductor device and bonding method thereof

CN122030002ACN 122030002 ACN122030002 ACN 122030002ACN-122030002-A

Abstract

An apparatus includes a backside support layer having a first thickness, an adhesive layer over the backside support layer, a metal layer over the adhesive layer, wherein the metal layer serves as a backside connector, a semiconductor substrate layer over the metal layer, wherein the semiconductor substrate active layer has a second thickness, and a plurality of front side connectors, wherein active circuitry in the semiconductor substrate layer is electrically coupled between the plurality of front side connectors and the metal layer.

Inventors

  • D. Wilcoxon

Assignees

  • 达尔科技股份有限公司

Dates

Publication Date
20260512
Application Date
20241018
Priority Date
20240911

Claims (20)

  1. 1. A method, comprising: providing a device wafer having a first side bonded to a support wafer, wherein the device wafer comprises a metal layer, a semiconductor substrate, a dielectric layer, and a plurality of connectors; Providing a carrier, wherein the carrier has a diameter that is the same as the diameter of the device wafer; applying an adhesive material to a second side of the device wafer to form a first adhesive layer; Applying the adhesive material to the carrier to form a second adhesive layer; performing a partial curing process on the first adhesive layer and the second adhesive layer; bonding the device wafer to the carrier by bonding the first adhesive layer and the second adhesive layer together, and A full cure process is performed on the adhesive material between the device wafer and the carrier.
  2. 2. The method according to claim 1, wherein: the support wafer is peeled from the device wafer after bonding the device wafer to the carrier wafer and before performing the full cure process on the adhesive material.
  3. 3. The method of claim 1 or claim 2, further comprising: After the full cure process is performed on the adhesive material, a dicing process is performed to separate the plurality of chips in the device wafer into a plurality of packages, wherein each of the plurality of packages includes a workpiece of the carrier.
  4. 4. A method according to claim 3, wherein: At a time after the dicing process has been performed, the work piece of the carrier is the outermost layer of the corresponding package.
  5. 5. The method of any one of claims 1-4, further comprising: performing the partial curing process at a first temperature on the second side of the device wafer and the adhesive material over the carrier; Bonding the device wafer to the carrier at a second temperature, and Performing the full cure process on the adhesive material at a third temperature, wherein: The third temperature being at least 100 degrees higher than the first temperature, and The first temperature is at least 100 degrees higher than the second temperature.
  6. 6. The method according to claim 5, wherein: the first temperature is about 140 degrees; the second temperature is about 30 DEG C The third temperature is about 260 degrees.
  7. 7. The method of any one of claims 1 to 6, wherein: the adhesive layer between the device wafer and the carrier has a first thickness prior to performing the full cure process on the adhesive material; After the full cure process is performed on the adhesive material, the adhesive layer between the device wafer and the carrier has a second thickness, and The metal layer has a third thickness, and wherein: the first thickness is greater than the third thickness, and The third thickness is greater than the second thickness.
  8. 8. The method of any one of claims 1 to 7, wherein: The adhesive material is a polyimide adhesive material.
  9. 9. The method of any one of claims 1 to 8, wherein: the metal layer is in direct contact with the semiconductor substrate, and The metal layer serves as a connector that is electrically coupled to active circuitry in the semiconductor substrate.
  10. 10. The method of any one of claims 1-9, further comprising: The device wafer is bonded to the carrier using liquid phase bonding under high pressure in a vacuum.
  11. 11. An apparatus, comprising: A backside support layer having a first thickness; an adhesive layer over the backside support layer; a metal layer over the adhesive layer, wherein the metal layer serves as a backside connector; A semiconductor substrate layer over the metal layer, wherein the semiconductor substrate layer has a second thickness, and A plurality of front side connectors, wherein active circuitry in the semiconductor substrate layer is electrically coupled between the plurality of front side connectors and the metal layer.
  12. 12. The device of claim 11, further comprising: a cover layer formed between the adhesive layer and the metal layer, and A passivation layer over the semiconductor substrate layer.
  13. 13. The apparatus of claim 11 or 12, wherein: The adhesive layer is formed of a polyimide adhesive material, wherein the polyimide adhesive material is semi-solid before a curing process is applied to the polyimide adhesive material.
  14. 14. The device of any one of claims 11-13, wherein: The first thickness of the backside support layer is at least four times the second thickness of the semiconductor substrate layer.
  15. 15. The device of any one of claims 11-14, wherein: the metal layer has a third thickness The adhesive layer has a fourth thickness, and wherein: the second thickness of the semiconductor substrate layer is greater than the third thickness of the metal layer, and The third thickness of the metal layer is greater than the fourth thickness of the adhesive layer.
  16. 16. An apparatus, comprising: A backside support layer having a first thickness; an adhesive layer over the backside support layer; a metal layer over the cap layer, wherein the metal layer has a second thickness, and A semiconductor substrate layer over the metal layer, wherein the semiconductor substrate layer has a third thickness, wherein: the first thickness of the backside support layer is at least four times the third thickness of the semiconductor substrate layer, and The third thickness of the semiconductor substrate layer is greater than the second thickness of the metal layer.
  17. 17. The apparatus of claim 16, wherein: the first thickness is in a range from about 200 μm to about 725 μm; The second thickness is about 30 μm, and The third thickness is about 50 μm.
  18. 18. The apparatus of claim 16 or 17, further comprising a cap layer formed between the adhesive layer and a metal layer, wherein: The metal layer is formed of copper, and The cap layer is formed of nickel.
  19. 19. The apparatus of any one of claims 16-18, further comprising: A passivation layer formed on the semiconductor substrate layer, and A plurality of connectors formed over the passivation layer.
  20. 20. The apparatus of claim 19, wherein: the semiconductor substrate layer includes a plurality of active circuits electrically coupled between the plurality of connectors and the metal layer.

Description

Power semiconductor device and bonding method thereof Cross reference to related applications This patent application claims priority to, and in particular is a continuation of, U.S. application Ser. No. 18/882,721, filed on Ser. No. 2024, 9, 11, and entitled "Power semiconductor apparatus and method of bonding (Power Semiconductor Apparatus and Bonding Method Thereof) thereof," which is hereby incorporated by reference as if fully set forth herein. Technical Field The present disclosure relates generally to the field of integrated circuits, and in particular embodiments, to techniques and mechanisms for thin wafer power semiconductor devices. Background Since the invention of integrated circuits, the semiconductor industry has experienced a rapid growth due to the ever-increasing integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). To a large extent, this increase in integration density results from repeated decreases in minimum feature size, which allows more components to be integrated into a given area. With the development of semiconductor technology, thin wafer semiconductor devices are becoming an effective alternative to further reduce the physical size of semiconductor chips. For example, thin wafer semiconductor devices are increasingly important in space-critical battery applications, such as in portable electronics and electric vehicles. These devices utilize ultra-thin silicon or other semiconductor materials to minimize thickness while maintaining high electrical performance. By reducing the wafer thickness, these semiconductors can be integrated into compact battery systems, enhancing energy density without compromising functionality. In semiconductor manufacturing processes, thin wafers face significant challenges due to their instability, lack of flatness, and susceptibility to breakage and stress during processing, all of which can negatively impact device quality. Unsupported thin wafers tend to have non-planar, wavy contours that make them unsuitable for subsequent fabrication processes requiring flat surfaces. In addition, when the thin wafer is not supported during the semiconductor assembly process, it can cause severe package warpage. This is because inherent stresses in thin wafers coupled with support structures can occur during packaging resulting in uneven force distribution. These stresses can become unbalanced as the wafer is processed, particularly when the wafer is released from its support or subjected to thermal cycling during assembly. This imbalance can lead to bending or warping of the entire package, which can affect the reliability of the final product, leading to problems such as poor electrical connections, impaired mechanical stability, and reduced overall performance of the semiconductor device. Thus, there is a clear need for a support assembly that can accommodate thin wafers within existing processing systems. The present disclosure addresses this need. Disclosure of Invention Technical advantages are generally achieved by embodiments of the present disclosure that describe thin wafer power semiconductor devices. According to an embodiment, a method includes providing a device wafer having a first side bonded to a support wafer, wherein the device wafer includes a metal layer, a semiconductor substrate, a dielectric layer, and a plurality of connectors, providing a carrier, wherein the carrier has a diameter that is the same as a diameter of the device wafer, applying an adhesive material to a second side of the device wafer to form a first adhesive layer, applying the adhesive material to the carrier to form a second adhesive layer, performing a partial curing process on the first adhesive layer and the second adhesive layer, bonding the device wafer to the carrier by bonding the first adhesive layer and the second adhesive layer together, and performing a full curing process on the adhesive material between the device wafer and the carrier. According to another embodiment, a device includes a backside support layer having a first thickness, an adhesive layer over the backside support layer, a metal layer over the adhesive layer, wherein the metal layer serves as a backside connector, a semiconductor substrate layer over the metal layer, wherein the semiconductor substrate layer has a second thickness, and a plurality of front side connectors, wherein active circuitry in the semiconductor substrate layer is electrically coupled between the plurality of front side connectors and the metal layer. According to yet another embodiment, an apparatus includes a backside support layer having a first thickness, an adhesive layer over the backside support layer, a metal layer over the cap layer, wherein the metal layer has a second thickness, and a semiconductor substrate layer over the metal layer, wherein the semiconductor substrate layer has a third thickness, wherein the first thickness of the backside support