CN-122030004-A - Method and structure for direct metal bonding using metal oxides

Abstract

A semiconductor element is provided over the conductive features at the hybrid bonding surface, with a microstructured metal oxide layer. The microstructured metal oxide layer comprises fine metal oxide particles, such as nanoparticles. The particles may be formed over the conductive features by oxidizing the metal included in the conductive features, or by providing a metal oxide over the conductive features. When directly bonded to another element, the microstructured metal oxide layer may form a strong bond at the bonding interface at a significantly reduced annealing temperature.

Inventors

• C.E. Youzo
• O.Zhao
• G.Z. Guevara
• D. Suvito
• G. G. Little Fuenten
• R. Carter Carr
• T. Walker man

Assignees

• 艾德亚半导体接合科技有限公司

Dates

Publication Date

20260512

Application Date

20240821

Priority Date

20231030

Claims (20)

1. 1. A method for hybrid bonding, comprising: providing a first element comprising a first dielectric material having a first bonding surface, a first conductive feature at least partially embedded in the first dielectric material, a metal oxide layer formed over the first conductive feature and exposed at the first bonding surface; Providing a second element comprising a second dielectric material having a second bonding surface, a second conductive feature at least partially embedded in the second dielectric material, and Bonding the first element directly to the second element includes bonding the first dielectric material directly to the second dielectric material with the metal oxide layer between the first conductive feature and the second conductive feature.
2. 2. The method of claim 1, wherein bonding the first dielectric material directly to the second dielectric material occurs at room temperature.
3. 3. The method of claim 1, further comprising annealing the first element and the second element at an annealing temperature to bond the first conductive feature directly to the second conductive feature.
4. 4. A method according to claim 3, wherein the metal of the metal oxide is copper and the annealing temperature is less than about 250 ℃.
5. 5. The method of claim 4, wherein the annealing temperature is less than about 200 ℃.
6. 6. The method of claim 4, wherein the annealing temperature is less than about 180 ℃.
7. 7. The method of claim 4, wherein the first conductive feature comprises one or more of copper, nickel, gold, indium, molybdenum, zinc, tungsten, tantalum, and titanium.
8. 8. The method of claim 4, wherein the second conductive feature comprises one or more of copper, nickel, gold, indium, molybdenum, zinc, tungsten, tantalum, and titanium.
9. 9. A microelectronic structure for low temperature hybrid bonding, comprising: a first bonding layer having a first upper surface prepared for hybrid bonding, the first bonding layer comprising: a first conductive feature having a metal oxide layer disposed thereon, the metal oxide layer being exposed at the first upper surface, and A first dielectric material surrounding the first conductive feature, the first dielectric material being exposed at the first upper surface.
10. 10. The microelectronic structure of claim 9, wherein the first conductive feature comprises one or more of copper, nickel, gold, indium, molybdenum, zinc, tungsten, tantalum, and titanium.
11. 11. The microelectronic structure of claim 10, wherein the first conductive feature is at least partially separated from the surrounding dielectric material, wherein the separation is at least partially effected by the metal oxide disposed.
12. 12. The microelectronic structure of claim 9, wherein the metal oxide layer comprises copper oxide.
13. 13. The microelectronic structure of claim 12, wherein the metal oxide layer has a thickness of at least about 20 nm a.
14. 14. The microelectronic structure of claim 9, wherein the first upper surface formed from the metal oxide layer has a surface roughness of at least 2 nm RMS.
15. 15. The microelectronic structure of claim 9, wherein the oxide layer comprises nanoparticles.
16. 16. The microelectronic structure of claim 15, wherein the nanoparticles have an average largest dimension in the range of about 2 nm to 100 nm.
17. 17. The microelectronic structure of claim 9, wherein the metal oxide layer is formed by oxidizing a metal of the first conductive feature.
18. 18. The microelectronic structure of claim 17, wherein the oxidation is plasma oxidation, thermal oxidation, ozone exposure, or wet oxidation with inorganic or organic peroxides.
19. 19. A bonding structure comprising: A first element comprising a first bonding layer, the first bonding layer comprising: A first dielectric material having a first upper surface, and A first conductive feature at least partially embedded in the first dielectric material at the upper surface; A second element comprising a second bonding layer, the second bonding layer comprising: A second dielectric material having a second upper surface, and A second conductive feature at least partially embedded in the second dielectric material at the second upper surface, and Wherein the first upper surface is directly bonded to the second upper surface at a bonding interface and the first conductive feature is directly bonded to the second conductive feature to form a bonding contact having an oxygen content of greater than 100 ppm in metal within about 100 nm of the bonding interface.
20. 20. The bonding structure of claim 19, wherein the second conductive feature comprises one or more of copper, nickel, gold, indium, molybdenum, zinc, tungsten, tantalum, and titanium.

Description

Method and structure for direct metal bonding using metal oxides Technical Field The present disclosure relates to direct bonding of microelectronic devices, and more particularly to direct metal bonding, such as hybrid bonding. Background The microelectronics industry has experienced tremendous growth over the past few decades. However, the market is never in the spotlight of the demand for faster connections between input/output (I/O) density and chips. This demand has driven Integrated Circuit (IC) system designs into three-dimensional architectures. Solder bumps and micro-bumps may provide vertical interconnection between chips by using small metal bumps on the die as a form of wafer level package. Hybrid bonding can provide a solution for the ultra-high density of interconnect features. Hybrid bonding, such as DBI ® technology commercially available from Adeia of San Jose, CA, avoids the use of metal bumps, but instead uses direct metal-to-metal (e.g., copper-to-copper) conductive feature connections to connect the die in the package. In the bonding layer of each bonding element, conductive features (such as metal contact pads) are embedded in a dielectric material. The hybrid bonding surface may be planarized and cleaned by Chemical Mechanical Polishing (CMP) to remove particles and contaminants. The plasma activation may create active sites on the dielectric material of the hybrid bonding surface of at least one of the two elements to be bonded. The two bonding elements are precisely aligned and bonded together in a bonding apparatus with active sites on the bonding surfaces bonded to each other. The dielectric bonding may be performed at room temperature. The annealing process may help bond aligned conductive features and may also strengthen the bond between dielectric materials. While hybrid bonding has greatly improved the ability to form high density and reliable connections between microelectronics, there remains a need for improved yields, reduced costs, and/or reduced thermal budget consumption. Drawings The detailed description will be described with reference to the following drawings, which are provided by way of example only and not by way of limitation. Fig. 1-4 are schematic cross-sectional views illustrating an example process for fabricating a semiconductor element having metal oxide on conductive features for hybrid bonding. Fig. 5-7B are schematic cross-sectional views illustrating an example process for hybrid bonding an element having a metal oxide on a conductive feature with another element. Fig. 8A is an Atomic Force Microscope (AFM) view showing the topography of the upper surface of an experimental die produced according to the process of fig. 1-4. Fig. 8B is a Transmission Electron Microscope (TEM) image showing a cross section of an experimental bonding structure produced according to the process of fig. 1-7B. FIG. 8C is an Energy Dispersive Spectroscopy (EDS) line scan across the bonding interface of the experimental bonding structure that produced the image of FIG. 8B. Fig. 9-14 are schematic cross-sectional views illustrating another example process for fabricating a semiconductor element having metal oxide on conductive features for hybrid bonding. Fig. 15A to 16 are schematic cross-sectional views of a bonding structure including the semiconductor element of fig. 14. Fig. 17-18 are schematic cross-sectional views illustrating another example process for fabricating a semiconductor element having metal oxide on conductive features for hybrid bonding. Fig. 19-21 are schematic cross-sectional views illustrating an example process of hybrid bonding a wafer having metal oxide on conductive features with another wafer. Fig. 22-26 are schematic cross-sectional views illustrating an example process for hybrid bonding a wafer with metal oxide on conductive features to multiple chips. Fig. 27-28 are schematic cross-sectional views illustrating example hybrid bonding structures with conductive features of different widths. Fig. 29 is a schematic cross-sectional view of two microelectronic elements configured to be hybrid bonded together. Fig. 30 is a schematic cross-sectional view of a bonding structure including two of the microelectronic elements of fig. 29. Detailed Description The annealing temperature and the annealing duration used to form the direct conductor-to-conductor (e.g., metal-to-metal) bond are critical in the manufacture of the direct bonded component. Lower annealing temperatures and/or shorter annealing durations may be desirable, for example, to reduce thermal budget consumption and reduce stress due to Coefficient of Thermal Expansion (CTE) mismatch. Various bond layer structures and methods for producing such bonded semiconductor elements may be implemented to achieve a lower annealing temperature to sufficiently fuse together contact pads or other conductive features of the bonded semiconductor elements. One way to reduce the annealing temperature includes p