Search

CN-224203593-U - Program-controlled resistance load circuit

CN224203593UCN 224203593 UCN224203593 UCN 224203593UCN-224203593-U

Abstract

The utility model relates to the technical field of circuits, in particular to a program-controlled resistance load circuit which comprises a power supply module, an optical coupler isolation module, a serial-parallel conversion module, a singlechip U5 and an adjusting resistance module, wherein the adjusting resistance module comprises a first adjusting resistance circuit and a second adjusting resistance circuit. In order to consider that the MOS tube has internal resistance, when more MOS tubes are connected in series, the generated resistance can be influenced to a certain extent, the utility model designs a first resistance circuit, the first resistor circuit replaces a plurality of MOS tubes of the second resistor circuit with one MOS tube, so that the influence caused by the internal resistances of the plurality of MOS tubes is reduced.

Inventors

  • WANG FENG

Assignees

  • 深圳智控佳科技有限公司

Dates

Publication Date
20260505
Application Date
20231230

Claims (10)

  1. 1. The program-controlled resistance load circuit is characterized by comprising a power supply module (1), an optical coupling isolation module (2), a serial-parallel conversion module (3), a singlechip U5 and an adjusting resistance module (4), wherein the output end of the power supply module (1) supplies power to the optical coupling isolation module (2), the serial-parallel conversion module (3), the singlechip U5 and the adjusting resistance module (4), the optical coupling isolation module (2) is electrically connected with the serial-parallel conversion module (3) to the singlechip U5, and the serial-parallel conversion module (3) is electrically connected with the singlechip U5 to the adjusting resistance module (4); The serial-parallel conversion module (3) comprises two parallel registers, namely a register U6 and a register U7, the regulating resistor module (4) comprises a first regulating resistor circuit (41) and a second regulating resistor circuit (42), the singlechip U5 is electrically connected with the first regulating resistor circuit (41), and the output ends of the two registers are electrically connected with the second regulating resistor circuit (42); The first regulating resistor circuit (41) comprises a plurality of first load branches formed by first MOS (metal oxide semiconductor) tubes, second MOS tubes and first resistors, wherein the second MOS tubes of each first load branch are connected in parallel with the first resistors and then connected in series with the first switch tubes, the second regulating resistor circuit (42) comprises a second load branch formed by a plurality of third MOS tubes and a plurality of second resistors, the second resistors are connected in series, each second resistor is connected in parallel with one third MOS tube, and two ends of each second MOS tube are connected in parallel with the branches of the plurality of second resistors.
  2. 2. A programmable resistive load circuit according to claim 1, wherein the power supply module (1) comprises an isolated power supply module and a voltage regulator U3, and the power supply module (1) is provided with a 9V output voltage and a 5V output voltage.
  3. 3. The programmable resistive load circuit according to claim 1, wherein the optocoupler isolation module (2) comprises a optocoupler U1 and an optocoupler U2, a pin 6 of the optocoupler U1 is electrically connected to a pin 1 of the single-chip microcomputer U5, and a pin 3 of the optocoupler U2 is electrically connected to a pin 2 of the single-chip microcomputer U5.
  4. 4. The program-controlled resistor load circuit according to claim 1, wherein the serial-parallel conversion module (3) is provided with a MOS tube Q23, a MOS tube Q26, a MOS tube Q29 and a MOS tube Q31, a pin 3 of the single-chip microcomputer U5 is electrically connected with a grid of the MOS tube Q23, a drain electrode of the MOS tube Q23 is connected with a resistor R23 in parallel and then is electrically connected with pins 1 of two registers, a pin 19 of the single-chip microcomputer U5 is electrically connected with a grid of the MOS tube Q26, a drain electrode of the MOS tube Q26 is connected with a resistor R27 in parallel and then is electrically connected with a pin 2 of the register U6, a pin 18 of the single-chip microcomputer U5 is electrically connected with a grid of the MOS tube Q29, a drain electrode of the MOS tube Q29 is electrically connected with a pin 3 of the two registers, a pin 17 of the single-chip microcomputer U5 is electrically connected with a grid of the MOS tube Q31, and a drain electrode of the MOS tube Q31 is connected with a resistor R31 in parallel.
  5. 5. The program-controlled resistor load circuit according to claim 1, wherein the first load branches are provided with five pins 12-16 of the single chip microcomputer U5 are respectively electrically connected with the five first load branches, the first MOS transistor comprises a MOS transistor Q24, a MOS transistor Q19, a MOS transistor Q15, a MOS transistor Q12 and a MOS transistor Q8, the second MOS transistor comprises a MOS transistor Q21, a MOS transistor Q18, a MOS transistor Q14, a MOS transistor Q10 and a MOS transistor Q6, and the first resistor comprises a resistor R24, a resistor R20, a resistor R17, a resistor R15 and a resistor R12.
  6. 6. The programmable resistor load circuit according to claim 5, wherein the pin 12 of the single-chip microcomputer U5 is electrically connected to the gate of the MOS transistor Q24, the drain parallel resistor R24 of the MOS transistor Q24 is electrically connected to the gate of the MOS transistor Q21, the pin 13 of the single-chip microcomputer U5 is electrically connected to the gate of the MOS transistor Q19, the drain parallel resistor R20 of the MOS transistor Q19 is electrically connected to the gate of the MOS transistor Q18, the pin 14 of the single-chip microcomputer U5 is electrically connected to the gate of the MOS transistor Q15, the drain parallel resistor R17 of the MOS transistor Q25 is electrically connected to the gate of the MOS transistor Q14, the pin 15 of the single-chip microcomputer U5 is electrically connected to the gate of the MOS transistor Q12, the drain parallel resistor R15 of the MOS transistor Q12 is electrically connected to the gate of the MOS transistor Q10, the pin 16 of the single-chip microcomputer U5 is electrically connected to the gate of the MOS transistor Q8, and the drain parallel resistor R12 of the MOS transistor Q8 is electrically connected to the gate of the MOS transistor Q6.
  7. 7. The programmable resistive load circuit according to claim 1, wherein the second resistor comprises resistors R1-R16, the third MOS transistor comprises MOS transistors Q1-Q5, MOS transistor Q7, MOS transistor Q9, MOS transistor Q11, MOS transistor Q13, MOS transistors Q16-Q17, MOS transistor Q20, MOS transistor Q22, MOS transistor Q25, MOS transistors Q27-Q28, and MOS transistor Q30, and the gate of each of the third MOS transistors is connected in parallel with a resistor and then grounded.
  8. 8. The program-controlled resistor load circuit according to claim 7, wherein the second resistors R1-R16 are connected in series, the resistor R1 is connected in series with a third MOS transistor Q30, the pin 11 of the single-chip microcomputer U5 is electrically connected to the gate of the MOS transistor Q30, the pin 4 of the register U6 is electrically connected to the gate rear parallel resistor R1 of the MOS transistor Q28, the pin 5 of the register U6 is electrically connected to the gate rear parallel resistor R2 of the MOS transistor Q27, the pin 6 of the register U6 is electrically connected to the gate rear parallel resistor R3 of the MOS transistor Q25, the pin 7 of the register U6 is electrically connected to the gate rear parallel resistor R4 of the MOS transistor Q22, the pin 14 of the register U6 is electrically connected to the gate rear parallel resistor R5 of the MOS transistor Q20, the pin 13 of the register U6 is electrically connected to the gate rear parallel resistor R6 of the MOS transistor Q17, the pin 12 of the register U6 is electrically connected to the gate rear parallel resistor R7 of the MOS transistor Q16, and the pin 11 of the register U6 is electrically connected to the gate rear parallel resistor R8 of the MOS transistor Q11.
  9. 9. The program-controlled resistor load circuit according to claim 7, wherein the pin 11 of the single chip microcomputer U5 is electrically connected to the gate of the MOS transistor Q30, the pin 4 of the register U7 is electrically connected to the gate back parallel resistor R9 of the MOS transistor Q11, the pin 5 of the register U7 is electrically connected to the gate back parallel resistor R10 of the MOS transistor Q9, the pin 6 of the register U7 is electrically connected to the gate back parallel resistor R11 of the MOS transistor Q7, the pin 7 of the register U7 is electrically connected to the gate back parallel resistor R12 of the MOS transistor Q5, the pin 14 of the register U7 is electrically connected to the gate back parallel resistor R13 of the MOS transistor Q3, the pin 13 of the register U7 is electrically connected to the gate back parallel resistor R15 of the MOS transistor Q1, and the pin 11 of the register U7 is electrically connected to the gate back parallel resistor R16 of the MOS transistor Q2.
  10. 10. The programmable resistor load circuit of claim 5 or 7, wherein the drain of the MOS transistor Q21 is electrically connected to the drain of the MOS transistor Q2, the source of the MOS transistor Q21 is electrically connected to the source of the MOS transistor Q28, the drain of the MOS transistor Q18 is electrically connected to the drain of the MOS transistor Q2, the source of the MOS transistor Q18 is electrically connected to the source of the MOS transistor Q25, the drain of the MOS transistor Q14 is electrically connected to the drain of the MOS transistor Q2, the source of the MOS transistor Q14 is electrically connected to the source of the MOS transistor Q20, the drain of the MOS transistor Q10 is electrically connected to the drain of the MOS transistor Q2, the source of the MOS transistor Q10 is electrically connected to the source of the MOS transistor Q16, the drain of the MOS transistor Q6 is electrically connected to the drain of the MOS transistor Q2, and the source of the MOS transistor Q6 is electrically connected to the source of the MOS transistor Q7.

Description

Program-controlled resistance load circuit Technical Field The utility model relates to the technical field of circuits, in particular to a program-controlled resistance load circuit. Background In electronic and electrical engineering, resistor boxes are often used to accurately measure resistance values and to achieve trimming of the resistance. The principle of the resistor box is to combine a plurality of fixed resistor elements together, and the total resistance value is changed by changing the connection mode of the elements. The connection relation between the elements can be changed by rotating or adjusting the controller of the resistor box, so that the continuous adjustment of the resistance value is realized. And partial regulation load resistance circuit appears on the market, and compared with the resistance box, this partial regulation load resistance circuit uses singlechip control, and is more accurate and stability is higher. A digital control variable resistor circuit (publication number: CN213874737U, publication date: 2021-08-03) comprises a power supply VCC, a voltage regulator LDO, an NTC analog port P1, a capacitor T2, a single chip microcomputer MCU, a resistor R1 and a four-way variable resistor module, wherein the positive input end IN+ of the NTC analog port P1 is connected with a ground signal GND, the power supply VCC is connected with a 3 pin of the voltage regulator LDO, the 2 pin of the voltage regulator LDO is connected with one end of the capacitor T1 through the resistor R1, the other end of the capacitor T1 is connected with the ground signal GND, the other end of the capacitor T1 is also connected with the single chip microcomputer MCU, the capacitor T1 is connected with the capacitor T2 IN parallel, and one end of the capacitor T1 is connected with the single chip microcomputer MCU. The circuit controls the level from the C1 end to the C40 end through the MCU so as to control the on or off of the MOS tube, thereby generating different resistance values, and realizing the automatic simulation temperature of the protection board test. Disclosure of utility model Aiming at the technical defects in the background technology, the utility model provides a program-controlled resistance load circuit, which solves the technical problems and meets the actual demands, and the specific technical scheme is as follows: the program-controlled resistance load circuit comprises a power supply module, an optocoupler isolation module, a serial-parallel conversion module, a singlechip U5 and an adjusting resistance module, wherein the output end of the power supply module supplies power to the optocoupler isolation module, the serial-parallel conversion module, the singlechip U5 and the adjusting resistance module, the optocoupler isolation module is electrically connected with the serial-parallel conversion module and the singlechip U5, and the serial-parallel conversion module is electrically connected with the singlechip U5 and the adjusting resistance module; The serial-parallel conversion module comprises two parallel registers, namely a register U6 and a register U7, wherein the adjusting resistance module comprises a first adjusting resistance circuit and a second adjusting resistance circuit, the singlechip U5 is electrically connected with the first adjusting resistance circuit, and the output ends of the two registers are electrically connected with the second adjusting resistance circuit; The first adjusting resistor circuit comprises a plurality of first load branches formed by first MOS (metal oxide semiconductor) tubes, second MOS tubes and first resistors, wherein the second MOS tubes of each first load branch are connected in parallel with the first resistors and then connected in series with the first switch tubes, the second adjusting resistor circuit comprises a second load branch formed by a plurality of third MOS tubes and a plurality of second resistors, the second resistors are connected in series, each second resistor is connected in parallel with one third MOS tube, and two ends of each second MOS tube are connected in parallel with a plurality of branches connected in series with the second resistors. As a further technical scheme of the utility model, the power supply module comprises an isolated power supply module and a voltage stabilizer U3, and the power supply module is provided with 9V output voltage and 5V output voltage. As a further technical scheme of the utility model, the optocoupler isolation module comprises a photoelectric coupler U1 and a photoelectric coupler U2, a pin 6 of the photoelectric coupler U1 is electrically connected with a pin 1 of the singlechip U5, and a pin 3 of the photoelectric coupler U2 is electrically connected with a pin 2 of the singlechip U5. As a further technical scheme of the utility model, the serial-parallel conversion module is provided with a MOS tube Q23, a MOS tube Q26, a MOS tube Q29 and a MOS tube Q31, a pin 3 of