CN-224203629-U - Bias circuit and chip

CN224203629UCN 224203629 UCN224203629 UCN 224203629UCN-224203629-U

Abstract

The utility model discloses a bias circuit and a chip, wherein the bias circuit comprises a first current mirror image unit, a first isolation tube, a second isolation tube and a current compensation unit, wherein the first current mirror image unit mirrors input current proportionally to generate a first mirror image current and a second mirror image current, the first isolation tube generates a first working current based on the first mirror image current, the second isolation tube generates a second working current based on the second mirror image current, the current compensation unit generates a compensation current based on the second working current and a second leakage current generated by the second isolation tube, and the current compensation unit compensates the first leakage current generated by the first isolation tube through the compensation current. According to the bias circuit and the chip, the first leakage current generated by the first isolation tube is compensated through the compensation current, so that the influence of the first leakage current of the first isolation tube on the output current of the bias circuit is greatly reduced or even eliminated.

Inventors

ZHOU SHIJIE
ZHOU XIANLI
WU DONGMING
YANG BINGZHONG

Assignees

思瑞浦微电子科技（苏州）股份有限公司

Dates

Publication Date: 20260505
Application Date: 20250513

Claims (10)

1. The bias circuit is characterized by comprising a first current mirror image unit, a first isolation tube, a second isolation tube and a current compensation unit, wherein the first current mirror image unit is used for mirroring input current in proportion to generate first mirror image current and second mirror image current, the first isolation tube is connected with the first current mirror image unit to generate first working current based on the first mirror image current, the second isolation tube is connected with the first current mirror image unit to generate second working current based on the second mirror image current, the current compensation unit is connected with the second isolation tube to generate compensation current based on the second working current and second leakage current generated by the second isolation tube, and the current compensation unit is connected with the first isolation tube to compensate the first leakage current generated by the first isolation tube through the compensation current.
2. The bias circuit of claim 1 further comprising a second current mirror unit coupled to the first isolation tube to mirror the compensated current in proportion to produce the output current.
3. The bias circuit of claim 1 wherein the first current mirror unit comprises a first transistor, a second transistor, and a third transistor, the control terminals of the first transistor, the second transistor, and the third transistor being coupled, the first terminal of the first transistor, the first terminal of the second transistor, and the first terminal of the third transistor being coupled to a ground voltage, the second terminal of the first transistor being coupled to the control terminal of the first transistor to receive an input current, the second terminal of the second transistor being coupled to the first terminal of the first isolation transistor, the second terminal of the third transistor being coupled to the first terminal of the second isolation transistor.
4. The bias circuit of claim 3 wherein the first, second and third transistors have a current mirror ratio of 1:m:n and M > N >0.
5. The bias circuit of claim 1 wherein the current compensation unit includes a fourth transistor and a fifth transistor, the control terminal of the fourth transistor, the second terminal of the fourth transistor, the control terminal of the fifth transistor being connected to the second terminal of the second isolation transistor, the first terminal of the fourth transistor and the first terminal of the fifth transistor being connected to the supply voltage, the second terminal of the fifth transistor being connected to the second terminal of the first isolation transistor.
6. The bias circuit of claim 2 wherein the second current mirror unit includes a sixth transistor and a seventh transistor, the first terminal of the sixth transistor and the first terminal of the seventh transistor being connected to the supply voltage, the second terminal of the sixth transistor, the control terminal of the seventh transistor being connected to the second terminal of the first isolation transistor, the second terminal of the seventh transistor being for generating the output current.
7. The bias circuit of claim 1, wherein the first current mirror unit and/or the current compensation unit is a Cascode current mirror.
8. The biasing circuit of claim 2, wherein the second current mirror unit is a Cascode current mirror.
9. The bias circuit of claim 5 wherein the current mirror ratio of said fourth and fifth transistors is 1:1.
10. A chip comprising the bias circuit of any one of claims 1-9.

Description

Bias circuit and chip Technical Field The utility model belongs to the technical field of integrated circuits, and particularly relates to a bias circuit and a chip. Background Many chips are used in high voltage systems, such as power chips, and the use of high voltage devices is particularly important in such chips, which are related to the main functions and reliability of the chip. The PN junction of the high voltage device can withstand higher voltages than the low voltage device, and the disadvantage is that the leakage current is larger, and especially in a high temperature environment, the non-ideal leakage current is unwilling for a chip designer, the influence caused by the non-ideal leakage current needs to be carefully considered, and the failure of many chips is often caused by the leakage of the high voltage device. The bias circuit is a reference of the chip, a high-voltage circuit and a low-voltage circuit are both required to be stable and accurate, the circuit part of the high-voltage chip is often divided into a high-voltage domain circuit and a low-voltage domain circuit, the bias circuit of the chip is generally manufactured under the low-voltage domain, the bias current is required to be provided for the high-voltage domain circuit through a conversion circuit, and leakage current brought by a high-voltage device used by the conversion circuit can influence the accuracy of the bias current, so that the function of the chip is influenced, and particularly, the chip is invalid under the conditions of high temperature environment or different process angles. The information disclosed in this background section is only for enhancement of understanding of the general background of the utility model and should not be taken as an acknowledgement or any form of suggestion that this information forms the prior art already known to a person of ordinary skill in the art. Disclosure of utility model The utility model aims to provide a bias circuit and a chip, which can eliminate the influence of leakage current on a circuit. In order to achieve the purpose, the technical scheme includes that the bias circuit comprises a first current mirror unit, a first isolation tube, a second isolation tube and a current compensation unit, wherein the first current mirror unit is used for mirroring input current in proportion to generate first mirror current and second mirror current, the first isolation tube is connected with the first current mirror unit to generate first working current based on the first mirror current, the second isolation tube is connected with the first current mirror unit to generate second working current based on the second mirror current, the current compensation unit is connected with the second isolation tube to generate compensation current based on the second working current and second leakage current generated by the second isolation tube, and the current compensation unit is connected with the first isolation tube to compensate the first leakage current generated by the first isolation tube through the compensation current. In one or more embodiments of the present utility model, the bias circuit further includes a second current mirror unit connected to the first isolation tube to mirror the compensated current in proportion to generate an output current. In one or more embodiments of the present utility model, the first current mirror unit includes a first transistor, a second transistor, and a third transistor, the control terminal of the first transistor, the control terminal of the second transistor, and the control terminal of the third transistor are connected, the first terminal of the first transistor, the first terminal of the second transistor, and the first terminal of the third transistor are connected to a ground voltage, the second terminal of the first transistor is connected to the control terminal of the first transistor to receive an input current, the second terminal of the second transistor is connected to the first terminal of the first isolation transistor, and the second terminal of the third transistor is connected to the first terminal of the second isolation transistor. In one or more embodiments of the utility model, the current mirror ratio of the first transistor, the second transistor, and the third transistor is 1:M:N, and M > N >0. In one or more embodiments of the present utility model, the current compensation unit includes a fourth transistor and a fifth transistor, the control terminal of the fourth transistor, the second terminal of the fourth transistor, and the control terminal of the fifth transistor are connected to the second terminal of the second isolation transistor, the first terminal of the fourth transistor and the first terminal of the fifth transistor are connected to the power supply voltage, and the second terminal of the fifth transistor is connected to the second terminal of the first isolation transistor. In one or more em