CN-224203634-U - Clock system and computer equipment

CN224203634UCN 224203634 UCN224203634 UCN 224203634UCN-224203634-U

Abstract

The embodiment of the application provides a clock system and computer equipment, wherein the clock system comprises a clock source circuit for generating multiple paths of clock signals, multiple clock buffers and at least one second clock signal, the multiple clock buffers comprise at least one first clock buffer, one first clock buffer is connected with one first clock signal in a butt joint mode, one first clock signal is expanded into multiple paths of computing unit clock signals and is provided for the multiple computing units in the butt joint mode, and the at least one second clock buffer is connected with one second clock signal in the butt joint mode, expands one second clock signal into multiple paths of interface exchange chip clock signals and provides the interface exchange chip in the butt joint mode. The clock system provided by the embodiment of the application can reduce the deployment cost.

Inventors

ZHANG JIANXING
YANG XIAOJUN
LIU SHENGJIE
Shi Jiucong
MA LONG

Assignees

海光信息技术股份有限公司

Dates

Publication Date: 20260505
Application Date: 20250514

Claims (10)

1. A clock system, characterized in that it is applied to a processor motherboard, said processor motherboard being provided with a plurality of computing units and a plurality of interface switching chips, said plurality of computing units being interconnected by said plurality of interface switching chips, said clock system comprising: The clock source circuit is used for generating multiple paths of clock signals, wherein the multiple paths of clock signals comprise at least one path of first clock signal and at least one path of second clock signal; a plurality of clock buffers comprising: At least one first clock buffer, wherein one first clock buffer is connected with one first clock signal in a butt joint mode, expands one first clock signal into a plurality of calculation unit clock signals, and provides the calculation unit clock signals for the butt joint mode; And at least one second clock buffer, wherein one second clock buffer is connected with one second clock signal in a butt joint mode, expands one second clock signal into a plurality of interface exchange chip clock signals, and provides the interface exchange chip clock signals for the butt joint mode.
2. The clock system of claim 1, wherein the interconnect interfaces of the plurality of computing units support the plurality of computing units to be interconnected through the plurality of interface switching chips, wherein the computing unit clock signals comprise a top layer interconnect clock signal and a bottom layer interconnect clock signal of the interconnect interfaces; the at least one first clock buffer includes: The clock buffer of the top-layer interconnection clock signal is used for butting one path of first clock signal, expanding the butted one path of first clock signal into multiple paths of top-layer interconnection clock signals corresponding to the multiple computing units and providing the multiple paths of top-layer interconnection clock signals for the butted computing units; And the clock buffer of the bottom interconnection clock signals is used for butting one path of first clock signals, expanding one path of butted first clock signals into multiple paths of bottom interconnection clock signals corresponding to the multiple computing units and providing the multiple paths of butted bottom interconnection clock signals for the multiple computing units.
3. The clock system of claim 2, wherein the computing unit clock signals further comprise wide area function link clock signals corresponding to wide area function links between the computing units; the at least one first clock buffer further comprises: The clock buffer of the wide area function link clock signal is used for butting one path of first clock signal, expanding one path of butted first clock signal into a plurality of paths of wide area function link clock signals corresponding to the plurality of computing units and providing the plurality of butted computing units.
4. The clock system of claim 2, wherein the interface switch chip clock signal comprises a system clock signal of the interface switch chip; The at least one second clock buffer includes: And the clock buffer of the system clock signal is used for butting one path of second clock signal, expanding one path of second clock signal to a plurality of paths of system clock signals corresponding to the plurality of interface exchange chips, and providing the plurality of interface exchange chips to be butted.
5. The clock system as recited in any one of claims 2-4, wherein the clock source circuit comprises: A crystal oscillator; And the clock generator is connected with the crystal oscillator and outputs the multipath clock signals based on the clock signals of the crystal oscillator.
6. The clock system of claim 1, wherein the compute unit clock signal comprises a PCIe clock signal for supporting a PCIe connection of the compute unit; The at least one first clock buffer includes a plurality of PCIe clock buffers; The PCIe clock buffer is connected with one path of first clock signal and is extended to PCIe clock signals, wherein the paths of the PCIe clock signals extended by the PCIe clock buffers correspond to the computing units, and the multi-path PCIe clock signals extended by the PCIe clock buffers are provided for the computing units.
7. The clock system of claim 6, further comprising a clock multiplexer; The clock multiplexer is used for butting one path of second clock signal and one PCIe clock buffer in the plurality of PCIe clock buffers, and outputting two paths of clock signals based on the one path of second clock signal which is in butting connection and one path of first clock signal which is received by the one PCIe clock buffer; The interface exchange chip clock signal comprises a reference clock signal of the interface exchange chip; The at least one second clock buffer includes: And the clock buffer for the reference clock signals is used for butting the clock multiplexer, expanding one path of clock signals output by the clock multiplexer into multiple paths of reference clock signals corresponding to the interface exchange chips, and providing the multiple paths of reference clock signals for the interface exchange chips.
8. The clock system as recited in claim 7, further comprising: A plurality of retimers connected to the clock multiplexer, the retimers receiving another clock signal , output by the clock multiplexer as a PCIe clock signal provided to the retimers; The multiple retimers are further connected with the multiple PCIe clock buffers, and receive PCIe clock signals of remaining paths of the multiple PCIe clock buffers, wherein the total number of paths of PCIe clock signals of one path and PCIe clock signals of the remaining paths corresponds to the number of the multiple retimers.
9. The clock system of claim 5, further comprising: the substrate management controller is connected with the clock generator, and the multipath clock signals also comprise one path of clock signals provided for the substrate management controller by the clock generator; The field programmable gate array is connected with the clock generator, and the multipath clock signals further comprise one path of system clock signal and one path of interface clock signal, wherein the one path of system clock signal and the one path of interface clock signal are provided for the field programmable gate array by the clock generator.
10. A computer device comprising a clock system as claimed in any one of claims 1 to 9.

Description

Clock system and computer equipment Technical Field The embodiment of the application relates to the technical field of processors, in particular to a clock system and computer equipment. Background The processor motherboard is the core circuit board of the computer system for interfacing and coordinating the hardware components on the processor motherboard to ensure operation and communication of the computer system. The clock signal is a periodically-changing pulse signal in the processor main board and is used for synchronizing and coordinating hardware components on the processor main board, so that the hardware components are ensured to run according to a preset time sequence and a preset speed, and the computer system can efficiently and stably execute tasks and process data. With the development of artificial intelligence technology, the demand for computing power is increasing, and a processor motherboard needs to be provided with a plurality of computing units and to realize interconnection between the plurality of computing units, so as to meet the demand for computing power with higher density. In this context, how to deploy a clock system of a processor motherboard and reduce the deployment cost is a technical problem that needs to be solved by those skilled in the art. Disclosure of utility model In view of the above, the embodiments of the present application provide a clock system and a computer device, which can reduce the deployment cost of the clock system of the processor motherboard. In order to achieve the above purpose, the embodiment of the present application provides the following technical solutions. In a first aspect, an embodiment of the present application provides a clock system applied to a processor motherboard, where the processor motherboard is provided with a plurality of computing units and a plurality of interface switching chips, and the plurality of computing units are interconnected by the plurality of interface switching chips, where the clock system includes: The clock source circuit is used for generating multiple paths of clock signals, wherein the multiple paths of clock signals comprise at least one path of first clock signal and at least one path of second clock signal; a plurality of clock buffers comprising: At least one first clock buffer, wherein one first clock buffer is connected with one first clock signal in a butt joint mode, expands one first clock signal into a plurality of calculation unit clock signals, and provides the calculation unit clock signals for the butt joint mode; And at least one second clock buffer, wherein one second clock buffer is connected with one second clock signal in a butt joint mode, expands one second clock signal into a plurality of interface exchange chip clock signals, and provides the interface exchange chip clock signals for the butt joint mode. Optionally, the interconnection interfaces of the plurality of computing units support the plurality of computing units to be interconnected through the plurality of interface switching chips, wherein the computing unit clock signals comprise a top interconnection clock signal and a bottom interconnection clock signal of the interconnection interfaces; the at least one first clock buffer includes: The clock buffer of the top-layer interconnection clock signal is used for butting one path of first clock signal, expanding the butted one path of first clock signal into multiple paths of top-layer interconnection clock signals corresponding to the multiple computing units and providing the multiple paths of top-layer interconnection clock signals for the butted computing units; And the clock buffer of the bottom interconnection clock signals is used for butting one path of first clock signals, expanding one path of butted first clock signals into multiple paths of bottom interconnection clock signals corresponding to the multiple computing units and providing the multiple paths of butted bottom interconnection clock signals for the multiple computing units. Optionally, the computing unit clock signal further comprises a wide area function link clock signal corresponding to a wide area function link between the computing units; the at least one first clock buffer further comprises: The clock buffer of the wide area function link clock signal is used for butting one path of first clock signal, expanding one path of butted first clock signal into a plurality of paths of wide area function link clock signals corresponding to the plurality of computing units and providing the plurality of butted computing units. Optionally, the interface exchange chip clock signal comprises a system clock signal of the interface exchange chip; The at least one second clock buffer includes: And the clock buffer of the system clock signal is used for butting one path of second clock signal, expanding one path of second clock signal to a plurality of paths of system clock signals corresponding to the plural