CN-224203685-U - Processor motherboard and computer device

Abstract

The embodiment of the application provides a processor main board and computer equipment, wherein the processor main board comprises a processor and at least one external equipment, the processor comprises a high-speed Serdes port used for connecting the at least one external equipment, the high-speed Serdes port comprises at least one communication interface mapped by a port bit wide range, one communication interface is connected with one external equipment, the port bit wide range comprises a plurality of port bits, the port bits are divided into independent connection bits and non-independent connection bits, one communication interface maps one independent connection bit or one connection bit range, the connection bit range comprises continuous independent connection bits, and/or continuous non-independent connection bits, and repeated port bits do not exist in different connection bit ranges. The embodiment of the application promotes the flexible configuration of the processor.

Inventors

• XU BIN
• LI JINGJING
• GUAN SHUYA
• ZHANG JIANXING

Assignees

• 海光信息技术股份有限公司

Dates

Publication Date

20260505

Application Date

20250514

Claims (10)

1. 1. A processor motherboard, comprising: A processor; At least one external device; The processor comprises a high-speed Serdes port for connecting with at least one external device, wherein the high-speed Serdes port comprises at least one communication interface mapped by a port bit wide range, and one communication interface is connected with one external device; Wherein one communication interface maps one independent connection bit or one connection bit range, which comprises consecutive independent connection bits and/or consecutive non-independent connection bits, and the different connection bit ranges have no repeated port bits.
2. 2. The processor motherboard of claim 1, wherein the independent connection bit is lower than the dependent connection bit in a bit sequence of the port bit wide range, wherein the bit range of the dependent connection bit supports a first bus type to support connection to an external device corresponding to the first bus type, and wherein the bit range of the independent connection bit supports multiple bus types to support connection to an external device corresponding to the multiple bus types, the multiple bus types including the first bus type.
3. 3. The processor motherboard of claim 2, wherein the at least one communication interface is embodied as one communication interface mapping a plurality of port bits of the port bit wide range; Or the at least one communication interface is specifically two communication interfaces with the same bus type, one communication interface maps continuous partial non-independent connection bits according to the sequence from high order to low order, and the other communication interface maps the rest non-independent connection bits and independent connection bits.
4. 4. A processor motherboard according to claim 3, wherein the bus type supported by the at least one communication interface is the first bus type.
5. 5. The processor motherboard of claim 2, wherein all independent connection bits form a connection bit range and all non-independent connection bits form a plurality of connection bit ranges; The number of the at least one communication interface is more than two, and one communication interface maps one connection bit range.
6. 6. The processor motherboard of claim 2 wherein said at least one communication interface is greater than two, an independent connection bit maps one communication interface, and consecutive non-independent connection bits form a plurality of connection bit ranges, each connection bit range maps one communication interface.
7. 7. The processor motherboard of claim 2, wherein the number of the at least one communication interface is greater than two, all independent connection bits form a plurality of connection bit ranges, all non-independent connection bits form a plurality of connection bit ranges, and one communication interface maps one connection bit range.
8. 8. The processor motherboard of claim 2, wherein the first bus type is a PCIe bus.
9. 9. The processor motherboard of any one of claims 1-8, wherein the wide range of port bits includes a plurality of port bits, specifically 16 port bits, the 16 port bits divided into 4 independent connection bits and 12 dependent connection bits.
10. 10. A computer device comprising a processor motherboard according to any of claims 1-9.

Description

Processor motherboard and computer device Technical Field The embodiment of the application relates to the technical field of processors, in particular to a processor main board and computer equipment. Background With rapid progress in technology, the electronic device industry is in a state of vigorous development. With the increasing functions of electronic devices, the functions of the processor serving as a core component of the electronic device are increasingly diversified. The processor needs to process a large amount of data operation, and also needs to support connection and communication of various external devices so as to meet the diversified demands of users. However, the interface design of the processor in the main board of the current processor is relatively single, which limits the flexible configuration of the processor. Therefore, how to provide a processor motherboard to promote flexible configuration of a processor is a technical problem that needs to be solved by those skilled in the art. Disclosure of utility model In view of the above, embodiments of the present application provide a processor motherboard and a computer device to promote flexible configuration of a processor. In order to achieve the above object, the embodiments of the present application provide the following technical solutions. In a first aspect, an embodiment of the present application provides a processor motherboard, including: A processor; At least one external device; The processor comprises a high-speed Serdes port for connecting with at least one external device, wherein the high-speed Serdes port comprises at least one communication interface mapped by a port bit wide range, and one communication interface is connected with one external device; Wherein one communication interface maps one independent connection bit or one connection bit range, which comprises consecutive independent connection bits and/or consecutive non-independent connection bits, and the different connection bit ranges have no repeated port bits. Optionally, the bit sequence of the independent connection bit in the wide range of the port bit is lower than the bit sequence of the dependent connection bit, the bit range of the dependent connection bit supports a first bus type to support connection with an external device corresponding to the first bus type, the bit range of the independent connection bit supports multiple bus types to support connection with an external device corresponding to the multiple bus types, and the multiple bus types comprise the first bus type. Optionally, the at least one communication interface is specifically a communication interface, and the one communication interface maps a plurality of port bits in the wide range of port bits; Or the at least one communication interface is specifically two communication interfaces with the same bus type, one communication interface maps continuous partial non-independent connection bits according to the sequence from high order to low order, and the other communication interface maps the rest non-independent connection bits and independent connection bits. Optionally, the bus type supported by the at least one communication interface is the first bus type. Optionally, all independent connection bits form a connection bit range, and all non-independent connection bits form a plurality of connection bit ranges; The number of the at least one communication interface is more than two, and one communication interface maps one connection bit range. Optionally, the number of the at least one communication interface is greater than two, one communication interface is mapped by one independent connection bit, a plurality of connection bit ranges are formed by continuous non-independent connection bits, and each connection bit range is mapped by one communication interface. Optionally, the number of the at least one communication interface is greater than two, all independent connection bits form a plurality of connection bit ranges, all non-independent connection bits form a plurality of connection bit ranges, and one communication interface maps one connection bit range. Optionally, the first bus type is PCIe bus. Optionally, the plurality of port bits included in the port bit wide range is specifically 16 port bits, and the 16 port bits are divided into 4 independent connection bits and 12 dependent connection bits. In a second aspect, an embodiment of the present application provides a computer device, including a processor motherboard as described in the first aspect above. The embodiment of the application provides a processor main board and computer equipment, wherein the processor main board comprises a processor and at least one external equipment, the processor comprises a high-speed Serdes port used for connecting the at least one external equipment, the high-speed Serdes port comprises at least one communication interface mapped by a port bit wide range, one communic