CN-224203687-U - Processor motherboard and computer device

CN224203687UCN 224203687 UCN224203687 UCN 224203687UCN-224203687-U

Abstract

The embodiment of the application provides a processor main board and computer equipment, wherein the processor main board comprises a plurality of computing acceleration entities, the computing acceleration entities are standardized entity units at least used for integrating computing units, the computing acceleration entities comprise computing units and first connectors, the computing units comprise a plurality of first ports, the first ports are respectively connected to a bottom board of the processor main board through the first connectors and support memory interconnection buses among the computing units, the bottom board comprises a plurality of first interconnection channels, one first interconnection channel is in butt joint with one first port of each of two computing acceleration entities, and the first interconnection channels cover interconnection among the computing acceleration entities. The processor motherboard provided by the embodiment of the application can provide a basis for data transmission among a plurality of computing units.

Inventors

Shi Jiucong
CHEN JIE
YANG XIAOJUN
LIU SHENGJIE

Assignees

海光信息技术股份有限公司

Dates

Publication Date: 20260505
Application Date: 20250514

Claims (10)

1. A processor motherboard, comprising: The system comprises a plurality of computing acceleration entities, a plurality of memory interconnection buses, a plurality of first interfaces and a plurality of second interfaces, wherein the computing acceleration entities are standardized entity units at least used for integrating computing units, and the computing acceleration entities comprise computing units and first connectors; A backplane comprising a plurality of first interconnect channels, one first interconnect channel interfacing one first port of each of two compute acceleration entities, and the plurality of first interconnect channels overlaying interconnects between the plurality of compute acceleration entities.
2. The processor motherboard of claim 1, wherein the two compute acceleration entities are connected by a single first interconnect channel or a combined first interconnect channel; the single first interconnection channel is a single first interconnection channel between two computing acceleration entities; the combined first interconnect channel includes at least two first interconnect channels between two compute acceleration entities.
3. The processor motherboard of claim 2, wherein the number of said first plurality of ports is greater than the number of said plurality of compute acceleration entities, wherein a first interconnect channel configured by one compute acceleration entity comprises: a single first interconnect channel and a plurality of sets of combined first interconnect channels, the number of sets of combined first interconnect channels being less than the number of the plurality of compute accelerating entities.
4. The processor motherboard of claim 3, wherein said plurality of compute acceleration entities is 4 compute acceleration entities, said first port is a high speed Serdes port, said plurality of first ports including a zeroth high speed Serdes port, a first high speed Serdes port, a second high speed Serdes port, a third high speed Serdes port, a fourth high speed Serdes port, a fifth high speed Serdes port, and a sixth high speed Serdes port; The first group of combined first interconnection channels and the second group of combined first interconnection channels are configured, and the one computing acceleration entity is respectively connected with two different computing acceleration entities through the first group of combined first interconnection channels and the second group of combined first interconnection channels; The first group of combined first interconnection channels comprise three first interconnection channels, which are respectively butted with a zeroth high-speed Serdes port, a first high-speed Serdes port and a second high-speed Serdes port of the computing acceleration entity, and a fifth high-speed Serdes port, a fourth high-speed Serdes port and a third high-speed Serdes port of the connected computing acceleration entity; The second group of combined first interconnection channels comprises three first interconnection channels, which are respectively butted with a third high-speed Serdes port, a fourth high-speed Serdes port and a fifth high-speed Serdes port of the one computing acceleration entity, and a second high-speed Serdes port, a first high-speed Serdes port and a zeroth high-speed Serdes port of the connected computing acceleration entity; the single first interconnect channel of the one compute acceleration entity configuration connects other compute acceleration entities than the two different compute acceleration entities, the single first interconnect channel interfacing with a sixth high speed Serdes port of the different compute acceleration entities.
5. The processor motherboard of claim 2, wherein the number of the plurality of first ports is less than the number of the plurality of compute acceleration entities, and the number of the plurality of first ports is the number of the plurality of compute acceleration entities minus one, and wherein the plurality of first interconnect lanes are each a single first interconnect lane.
6. The processor motherboard of claim 5, wherein the plurality of compute acceleration entities is 8 compute acceleration entities, the first port is a high speed Serdes port, the plurality of first ports comprises a zeroth high speed Serdes port, a first high speed Serdes port, a second high speed Serdes port, a third high speed Serdes port, a fourth high speed Serdes port, a fifth high speed Serdes port, and a sixth high speed Serdes port; one computational acceleration entity is connected one-to-one with the other seven computational acceleration entities through the single first interconnect channel.
7. The processor motherboard of claim 1, wherein the computing units further comprise a second port connected to a backplane of the processor motherboard through the first connector, the second port supporting a wide area functional link bus between computing units; the backplane also includes a plurality of second interconnect channels, one of which interfaces with a respective second port of two compute acceleration entities.
8. The processor motherboard of claim 7, wherein the plurality of compute acceleration entities are arranged in a row, and wherein the second ports of the compute acceleration entities are sequentially interfaced through a second interconnect channel, and wherein the second ports of the compute acceleration entities are interfaced end-to-end through the second interconnect channel.
9. The processor motherboard of claim 1, wherein said computing unit further comprises a third port and a fourth port, said third port supporting a PCIe bus and a memory interconnect bus between said computing unit; The processor motherboard further comprises a PCIe retimer and a second connector; The third port is connected to the bottom plate of the processor main board through the first connector, is connected with a PCIe retimer through a PCIe retimer connecting channel of the bottom plate, and is connected with other main boards through a second connector.
10. A computer device comprising a processor motherboard according to any of claims 1-9.

Description

Processor motherboard and computer device Technical Field The embodiment of the application relates to the technical field of processors, in particular to a processor main board and computer equipment. Background The processor motherboard is a core hardware platform of the computer system and is used for mainly connecting an IP (Intellectual Property ) component such as a computing unit and a processor of the computer system, and further, the processor motherboard is also used for connecting a memory, a storage bus, other various controllers, expansion cards and the like of the computer system. The computing unit is an IP component designed in the computer system for performing a specific computing task, for example, taking the computing unit as a depth computing unit, where the depth computing unit is an IP component dedicated to performing a deep learning task and a machine learning task in the computer system. With the development of integrated circuit design technology, more and more IP components are on a processor motherboard, and correspondingly, the processor motherboard may have multiple computing units thereon, where the computing units need to process a large amount of data and perform high-speed data exchange, so efficient interconnection between the multiple computing units and other components of the processor motherboard is particularly important. In this context, how to meet the interconnection requirements between multiple computing units in the design of a processor motherboard is a technical problem that needs to be solved by those skilled in the art. Disclosure of utility model In view of the above, the embodiments of the present application provide a processor motherboard and a computer device to meet the interconnection requirements between a plurality of computing units, and provide a basis for data transmission between the computing units. In order to achieve the above object, the embodiments of the present application provide the following technical solutions. In a first aspect, an embodiment of the present application provides a processor motherboard, including: The system comprises a plurality of computing acceleration entities, a plurality of memory interconnection buses, a plurality of first interfaces and a plurality of second interfaces, wherein the computing acceleration entities are standardized entity units at least used for integrating computing units, and the computing acceleration entities comprise computing units and first connectors; A backplane comprising a plurality of first interconnect channels, one first interconnect channel interfacing one first port of each of two compute acceleration entities, and the plurality of first interconnect channels overlaying interconnects between the plurality of compute acceleration entities. Optionally, the two computing acceleration entities are connected through a single first interconnection channel or a combined first interconnection channel; the single first interconnection channel is a single first interconnection channel between two computing acceleration entities; the combined first interconnect channel includes at least two first interconnect channels between two compute acceleration entities. Optionally, the number of the plurality of first ports is greater than the number of the plurality of computing acceleration entities, and the first interconnection channel configured by one computing acceleration entity comprises: a single first interconnect channel and a plurality of sets of combined first interconnect channels, the number of sets of combined first interconnect channels being less than the number of the plurality of compute accelerating entities. The first port is a high-speed Serdes port, and the plurality of first ports comprises a zero-high-speed Serdes port, a first high-speed Serdes port, a second high-speed Serdes port, a third high-speed Serdes port, a fourth high-speed Serdes port, a fifth high-speed Serdes port and a sixth high-speed Serdes port; The first group of combined first interconnection channels and the second group of combined first interconnection channels are configured, and the one computing acceleration entity is respectively connected with two different computing acceleration entities through the first group of combined first interconnection channels and the second group of combined first interconnection channels; The first group of combined first interconnection channels comprise three first interconnection channels, which are respectively butted with a zeroth high-speed Serdes port, a first high-speed Serdes port and a second high-speed Serdes port of the computing acceleration entity, and a fifth high-speed Serdes port, a fourth high-speed Serdes port and a third high-speed Serdes port of the connected computing acceleration entity; The second group of combined first interconnection channels comprises three first interconnection channels, which are respectively butted with a third high-sp