CN-224203693-U - Edge calculation box circuit structure

Abstract

The utility model provides an edge computing box circuit structure, which comprises a double-sided PCB substrate, a front partition provided with a communication control area, a back partition provided with a power supply storage area, a front layout, a Central Processing Unit (CPU) and a 4G communication module, wherein the upper left corner is provided with a SIM card seat and the 4G communication module, the CPU is 10+/-2 mm away from the edge of the 4G communication module, 4 paths of relays are arranged on the right side in parallel, each path of relay driving circuit is directly connected with a GPIO pin of the processor, a digital input interface, an analog input interface, an RS485 interface and an output interface are integrated at the upper end, the power supply interface is adjacent to a DC-DC conversion chip, and an LED indicator lamp, a debugging interface, a serial port, a USB interface and an Ethernet interface are integrated at the lower end.

Inventors

• LI ZHAOXIONG
• WU XINGYI
• LIU HUI
• ZHANG CHAOYANG

Assignees

• 福建省农业科学院资源环境与土壤肥料研究所

Dates

Publication Date

20260505

Application Date

20250807

Claims (1)

1. 1. An edge computing box circuit structure, characterized by: A double-sided PCB substrate, the front side is provided with a communication control area in a partition mode, the back surface is provided with a power supply storage area in a partition mode; The front layout comprises a SIM card seat and a 4G communication module arranged at the left upper corner, a Central Processing Unit (CPU) 10+/-2 mm away from the edge of the 4G communication module, 4 paths of relays arranged in parallel at the right side, wherein each path of relay driving circuit is directly connected with a processor GPIO pin, a digital input interface, an analog input interface, an RS485 interface and an output interface are integrated at the upper end, a power interface is adjacent to a DC-DC conversion chip, an AXP221S power management chip outputs three paths of voltage stabilization, namely, 1.2V/3A wiring length is less than or equal to 20mm to a processor core, 1.8V/2A is connected with a memory chip through pi-type filtering, an eMMC memory chip and DDR3 memory, and an LED indicator lamp, a debugging interface, a serial port, a USB interface, an Ethernet interface and a power interface are integrated at the lower end; The reverse layout comprises a LoRa communication module arranged at the position corresponding to the upper left corner and the 4G communication module, an on-board battery arranged at the lower right corner, a processor interconnection architecture comprising Quan Zhi A40i-H PCIe x1 channels directly connected with A4G communication module Mini PCIe socket, an Ethernet circuit comprising a processor RMII interface connected with an RTL8201F-VB-CG chip through a 22 omega impedance matching resistor, a network transformer center tap connected with a 0.1 mu F decoupling capacitor, an RS-485 interface connected with a processor UART1 port through an SN65HVD75DR chip, a signal line A/B connected with TVS tubes D1-D4 in parallel, an RS-232 interface connected with a processor UART2 port through an MAX3232ESE chip (U17), an analog input interface connected with a processor SPI bus through an ADC0832 analog input interface, an AXP221S power management chip pin connected with a 12V direct current input interface, a VBAT pin connected with a lithium battery interface, an ENLE pin connected with an full-VB 1 pin of a full-H processor, an RT8279GSP chip connected with a 12V input end connected with a 3V input end of the power amplifier through a power amplifier, a three-phase switch chip, a three-channel LED chip connected with a power amplifier, and a three-channel LED bridge 3D 3E 2 interface connected with a power amplifier, and a power amplifier 3E 3D 3E interface connected with a power amplifier, a CPI 2 interface, a power amplifier, and a power amplifier 3D 3E interface connected with a power amplifier, and a power amplifier 3.

Description

Edge calculation box circuit structure Technical Field The utility model relates to the technical field of edge calculation of the Internet of things, in particular to an edge calculation box circuit structure. Background With the rapid development of internet of things (IoT), 5G, artificial Intelligence (AI) and cloud computing, the agricultural internet of things is rapidly developed, however, with the increase of sensors of the internet of things, large-scale and fine management operations can lead to a large amount of environmental monitoring data, if intelligent control is required to be realized through a remote server, server pressure can be increased, problems of large data transmission amount, transmission delay and the like are caused, more bandwidth cost is generated, and the development goals of accurate control and efficient resource utilization in accurate agriculture cannot be met. The traditional agricultural Internet of things system relies on a cloud server to process sensor data, and has the problems of large data transmission delay, high bandwidth cost, poor instantaneity and the like. The existing edge computing equipment often has the defects of single interface, poor power supply adaptability, insufficient industrial environment compatibility and the like. Disclosure of Invention Therefore, the present utility model aims to provide an edge computing box circuit structure capable of performing computation and processing on an edge side of data generation, effectively reducing cloud pressure, improving real-time performance and reliability of a system, improving interface expansion capability and reducing signal interference. The utility model is implemented by a method of edge computing box circuit architecture, A double-sided PCB substrate, the front side is provided with a communication control area in a partition mode, the back surface is provided with a power supply storage area in a partition mode; The front layout comprises a SIM card seat and a 4G communication module arranged at the left upper corner, a Central Processing Unit (CPU) 10+/-2 mm away from the edge of the 4G communication module, 4 paths of relays arranged in parallel at the right side, wherein each path of relay driving circuit is directly connected with a processor GPIO pin, a digital input interface, an analog input interface, an RS485 interface and an output interface are integrated at the upper end, a power interface is adjacent to a DC-DC conversion chip, an AXP221S power management chip outputs three paths of voltage stabilization, namely, 1.2V/3A wiring length is less than or equal to 20mm to a processor core, 1.8V/2A is connected with a memory chip through pi-type filtering, an eMMC memory chip and DDR3 memory, and an LED indicator lamp, a debugging interface, a serial port, a USB interface, an Ethernet interface and a power interface are integrated at the lower end; and the reverse layout is that LoRa communication modules are arranged at the positions of the upper left corner and the 4G communication modules, and on-board batteries are arranged at the lower right corner. Furthermore, the processor interconnection architecture comprises Quan Zhi A40i-H PCIe x1 channels directly connected with A4G communication module Mini PCIe socket, and an Ethernet circuit, wherein a processor RMII interface is connected with an RTL8201F-VB-CG chip through a 22 omega impedance matching resistor, and a network transformer center tap is connected with a 0.1 mu F decoupling capacitor. Furthermore, the RS-485 interface is connected with the port of the processor UART1 through an SN65HVD75DR chip, TVS tubes D1-D4 are connected in parallel between signal wires A/B, the RS-232 interface is connected with the port of the processor UART2 through an MAX3232ESE chip (U17), and the analog input interface is connected with the SPI bus of the processor through an ADC0832 analog-to-digital converter. Further, the VIN pin of the AXP221S power management chip is connected with a 12V direct current input interface, the VBAT pin is connected with a lithium battery interface, the ENABLE pin is connected with a GPIO1 pin of a full-scale A40i-H processor, the VIN end of the RT8279GSP chip is connected with a 12V input, the output end is divided into two paths, wherein the first path outputs 5V_Relay to a relay array through an L1 inductor and the second path outputs 3.3V_MCU to the processor, the coil end of the 4-path relay is connected with a processor GPIO group through a ULN2803 driving chip, the contact end is connected with an output interface, the 4G module is connected with a processor PCIe bus through a Mini-PCIE socket, and the RTL8201F-VB-CG Ethernet PHY chip is connected with the processor through a RMII interface. Furthermore, the enable end EN of the RT8279GSP chip is connected to the GPIO2 pin of the processor, and the feedback end FB thereof sets the output voltage through the resistor divider network R1/R2. Furthermore, RE/D