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CN-224205111-U - Digital twin data management device

CN224205111UCN 224205111 UCN224205111 UCN 224205111UCN-224205111-U

Abstract

The utility model discloses a digital twin data management device belongs to industry thing networking data management technical field. The multi-protocol conversion chip is compatible with RS485, ethernet and optical fiber interfaces, the PCIe interface is adopted to realize high-speed data interaction of the processing module, the security module and the storage module, the dual redundancy circuit is utilized to ensure the reliability of check signal transmission, the hierarchical management of data is realized by combining a hierarchical storage architecture (SSD cache layer, RAID6 disk array layer and distributed node layer), and the data integrity is ensured by a model check unit (dual-precision floating point residual calculation) and a self-checking unit (CRC check and heartbeat packet detection) of the synchronous check module. The method has the beneficial effects that protocol conversion delay is less than or equal to 2 mu s, encryption throughput of SM4 algorithm reaches 5Gbps, RAID6 double-disk fault tolerance is realized, parameter updating batch processing efficiency is improved by 2 times, system availability is more than or equal to 99.999%, and digital twin data management requirements of high real-time, high safety and high reliability in industrial scenes are met.

Inventors

  • ZHANG ZHIRONG

Assignees

  • 张志荣

Dates

Publication Date
20260505
Application Date
20250430

Claims (10)

  1. 1. The digital twin data management device is characterized by comprising a data interface module (1), a processing module (2), a safety module (3), a storage module (4) and a synchronous verification module (5), wherein the data interface module (1) is connected with the input end of the processing module (2) through a data bus (6), the output end of the processing module (2) is respectively connected with the safety module (3) and the storage module (4) through a PCIe interface (7), the synchronous verification module (5) is simultaneously connected with the processing module (2) and the safety module (3) through a double redundancy circuit (8), the data interface module (1) comprises an RS485 physical interface (11), an Ethernet interface (12) and an optical fiber channel interface (13), and three sets of interfaces are connected in parallel to a bus converter (14).
  2. 2. The digital twin data management device according to claim 1, wherein the processing module (2) is internally integrated with a data cleaning unit (21), a heterogeneous converter (22) and a real-time synchronization unit (23), the input end of the data cleaning unit (21) is connected with the differential signal output end of the bus converter (14), and the output end of the data cleaning unit (21) is connected with the register input end of the heterogeneous converter (22) through an IO pin of the FPGA chip (24).
  3. 3. The digital twin data management device according to claim 2, wherein the heterogeneous converter (22) is composed of a protocol parsing subunit (221), a timestamp calibration subunit (222) and a format encoding subunit (223) in series, wherein the protocol parsing subunit (221) comprises a parallel structure of a Modbus parsing circuit (2211), an OPCUA parsing circuit (2212) and an MQTT parsing circuit (2213).
  4. 4. The digital twin data management apparatus according to claim 2, wherein the real-time synchronization unit (23) comprises an edge computing node (231) and a 5G communication module (232), the GPIO port (2311) of the edge computing node (231) is connected with the data pin of the 5G communication module (232) through an SPI interface (233), and a clock calibration circuit (234) is arranged in the edge computing node (231), wherein the crystal oscillation frequency of the clock calibration circuit is 24MHz + -50 ppm.
  5. 5. The digital twin data management device according to claim 1, wherein the security module (3) is composed of a hardware encryption engine (31) and an access control unit (32), the hardware encryption engine (31) adopts an ASIC chip (311) of a national encryption SM4 algorithm, the data throughput is 5Gbps + -5%, and the access control unit (32) comprises a physical isolation relay (321) and a digital certificate verification circuit (322).
  6. 6. The digital twin data management device according to claim 1, wherein the storage module (4) adopts a layered storage architecture and comprises an SSD cache layer (41), a disk array layer (42) and a distributed storage node layer (43), the SSD cache layer (41) is connected with the processing module (2) through an NVMe protocol interface (44), the disk array layer (42) adopts a RAID6 redundant structure (45), and the distributed storage node layer (43) comprises 3-5 storage nodes (46).
  7. 7. The digital twin data management apparatus according to claim 1, wherein the synchronization verification module (5) comprises a model verification unit (51) and an increment learning unit (52), the model verification unit (51) is composed of a residual calculation circuit (511) and a threshold comparator (512) which are connected in parallel, and the operation precision of the residual calculation circuit (511) is in an IEEE754 double-precision floating point format.
  8. 8. The digital twin data management device according to claim 7, wherein the incremental learning unit (52) comprises a parameter update queue (521) and a model version controller (522), the parameter update queue (521) has a depth of 64 to 256 parameter groups, and the model version controller (522) triggers the check signal by a version number generating circuit (523).
  9. 9. The digital twin data management device according to claim 1, wherein the bus converter (14) adopts a multi-protocol conversion chip (141) with an input impedance of 120Ω+ -2%, an output level range of 0-3V, and a signal conversion delay of 2 μs or less.
  10. 10. The digital twin data management device according to claim 1, wherein the dual redundancy circuit (8) is composed of two independent signal channels (82), each channel comprises a photoelectric isolator (83) and a differential amplifier (84), the insulation withstand voltage of the photoelectric isolator (83) is more than or equal to 2500Vrms, and the gain adjustable range of the differential amplifier (84) is 10-100 times.

Description

Digital twin data management device Technical Field The utility model belongs to the technical field of industrial Internet of things data management, and particularly relates to a digital twin data management device. Background The digital twin technology is increasingly widely applied in the field of industrial Internet of things, but the data management thereof faces the following technical bottlenecks: 1. The existing system (although supporting interfaces such as RS485 and Ethernet, protocol conversion delay is generally more than 5 mu s, and the lack of fiber channel support leads to low access efficiency of heterogeneous equipment; 2. the security capacity is weak, the traditional encryption scheme relies on software to realize a national encryption algorithm, the throughput is only 1-2Gbps, the industrial real-time data encryption requirement cannot be met, and a physical isolation mechanism is absent; 3. The reliability of the storage architecture is poor, the fault tolerance of the single-layer storage architecture is insufficient, the RAID5 reconstruction speed is low (less than or equal to 500 GB/h), and the requirements of cache and persistent storage cannot be met; 4. The data verification precision is low, the existing verification method (such as a model verification system of CN 112527876A) adopts single-precision floating point calculation, the error is more than or equal to 1 multiplied by 10 -6, a self-checking mechanism is lacked, and millisecond data abnormality is difficult to detect. As known by those skilled in the art, the above defects cause the problems of high data packet loss rate (more than or equal to 0.1 percent), low safety protection level (IP 20), insufficient storage availability (less than or equal to 99.9 percent) and the like in the scenes of intelligent manufacturing, smart cities and the like of the digital twin system. In view of this, there is a need for a digital twin data management device that integrates high throughput protocol conversion, hardware-level security encryption, multi-level fault-tolerant storage and high-precision dynamic verification, so as to meet the requirements of industrial-level real-time (delay less than or equal to 1 ms), security (encryption strength greater than or equal to 128 bits) and reliability (availability greater than or equal to 99.999%). Disclosure of utility model The technical problem to be solved is that the existing digital twin system has the problems of low data transmission efficiency, poor protocol compatibility and insufficient safety storage capacity. The digital twin data management device comprises a data interface module, a processing module, a safety module, a storage module and a synchronous verification module, wherein the data interface module is connected with the input end of the processing module through a data bus, the output end of the processing module is respectively connected with the safety module and the storage module through a PCIe interface, the synchronous verification module is simultaneously connected with the processing module and the safety module through a double redundancy circuit, the data interface module comprises an RS485 physical interface, an Ethernet interface and an optical fiber channel interface, and three interfaces are connected in parallel to an access bus converter. The method has the beneficial effects of realizing multi-protocol compatibility (RS 485/Ethernet/optical fiber), high-speed data transmission (PCIe interface), safe data storage (separation of a safety module and a storage module) and real-time verification (double redundant circuits). The working principle is that data is accessed to the bus converter uniformly through the multi-protocol interface, and after being cleaned and converted by the processing module, the data is shunted and forwarded to the security module for encryption or the storage module for persistence, and the synchronous verification module ensures the data consistency through the double-channel redundancy design. Under the preferred implementation condition, the technical problems to be solved are that the data processing capacity and the protocol conversion efficiency are improved. According to the technical scheme, a data cleaning unit, a heterogeneous converter and a real-time synchronization unit are integrated in the device, the input end of the data cleaning unit is connected with the differential signal output end of the bus converter, and the output end of the data cleaning unit is connected with the input end of a register of the heterogeneous converter through an IO pin of the FPGA chip. The FPGA acceleration data cleaning (delay is less than or equal to 2 mu s), and the heterogeneous converter supports multi-protocol dynamic analysis. The working principle is that the bus converter outputs differential signals to the data cleaning unit for filtering, and the FPGA processes data in parallel and then pushes the data to the heterogeneo