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CN-224205311-U - Substrate board

CN224205311UCN 224205311 UCN224205311 UCN 224205311UCN-224205311-U

Abstract

The application provides a substrate, which comprises a base layer, a stacking structure and a graphene layer, wherein the base layer is provided with a front surface and a back surface which are oppositely arranged, the stacking structure is at least positioned on the front surface of the base layer, the graphene layer is at least positioned on the surface of the stacking structure, which is away from the substrate, the stacking structure comprises at least two stress buffer layers, the thermal expansion coefficient of each stress buffer layer is between that of the base layer and that of the graphene layer, and the thermal expansion coefficient of the stress buffer layer which is closer to the base layer is larger. According to the application, the graphene layer can rapidly dissipate heat, the heat dissipation performance of the substrate is improved, the working temperature of devices on the board is reduced, the stability is improved, a thermal expansion coefficient transition region is formed between the graphene layer and the base layer by utilizing at least two stress buffer layers, the thermal stress concentration can be reduced, the problems of bonding layer fracture, interface stripping or substrate cracking/deformation and the like are reduced, the service life of the substrate is prolonged, the stress buffer layers can also assist in heat dissipation, and the heat dissipation efficiency of the substrate is further improved.

Inventors

  • LIU ZHIYONG
  • LIN DESHUN
  • ZHAO WEI
  • LIU YUHUA
  • Zhai Weixiong
  • HE HONGMEI
  • LI JUNDONG

Assignees

  • 鸿利智汇集团股份有限公司

Dates

Publication Date
20260505
Application Date
20250528

Claims (10)

  1. 1. A substrate characterized by comprising a base layer (100), a stacked structure (200) and a graphene layer (300), the base layer (100) having oppositely disposed front and back sides, the stacked structure (200) being located at least on the front side of the base layer (100), the graphene layer (300) being located at least on a surface of the stacked structure (200) facing away from the base layer (100); The stacked structure (200) comprises at least two stress buffer layers, each having a coefficient of thermal expansion that is between that of the base layer (100) and that of the graphene layer (300), and the closer to the base layer (100) the coefficient of thermal expansion of the stress buffer layer is greater.
  2. 2. The substrate of claim 1, wherein the stress buffer layer comprises a stacked first stress buffer layer (201) and at least one second stress buffer layer, the first stress buffer layer (201) being closer to the base layer (100) than the second stress buffer layer, the first stress buffer layer (201) being of non-porous structure, or the first stress buffer layer (201) having at least one first through hole (200 a) therein, the second stress buffer layer having at least one second through hole (200 b) therein; the aperture of the first through hole (200 a) is larger than that of the second through hole (200 b), the porosity of the first stress buffer layer (201) is smaller than that of the second stress buffer layer, and the closer to the second stress buffer layer of the base layer (100), the larger the aperture of the second through hole (200 b) is, the smaller the porosity is.
  3. 3. The substrate according to claim 2, wherein at least part of the second through holes (200 b) in two adjacent second stress buffer layers are in communication with each other and/or at least part of the first through holes (200 a) in the first stress buffer layer (201) are in communication with at least part of the second through holes (200 b) in the adjacent second stress buffer layers.
  4. 4. The substrate according to claim 2, wherein the first through-hole (200 a) is a constant diameter hole, or the aperture of the first through-hole (200 a) gradually increases in a direction approaching the base layer (100), and the minimum aperture of the first through-hole (200 a) is 20% or more of the maximum aperture thereof, and The second through hole (200 b) is a constant diameter hole, or the aperture of the second through hole (200 b) gradually increases along the direction approaching the base layer (100), and the minimum aperture of the second through hole (200 b) is greater than or equal to 20% of the maximum aperture thereof.
  5. 5. The substrate according to claim 2, wherein the base layer (100) is made of aluminum, the second stress buffer layer has three layers, the first layer to the third layer are sequentially stacked on the surface of the first stress buffer layer (201) facing away from the base layer (100), the thermal expansion coefficient of the first stress buffer layer (201) is 16×10 -6 /K～18×10 -6 /K, and the thermal expansion coefficients of the first layer to the third layer are 12×10 -6 /K～14×10 -6 /K、9×10 -6 /K～10×10 -6 /K and 7×10 -6 /K～8×10 -6 /K, respectively.
  6. 6. The substrate according to claim 2 or 5, wherein the second stress buffer layer has three layers, the first layer to the third layer are sequentially stacked on the surface of the first stress buffer layer (201) facing away from the base layer (100), the apertures of the first layer to the third layer are respectively 200nm to 500nm, 50nm to 200nm and 10nm to 50nm, and the porosities are respectively 10% -20%, 20% -30% and 30% -50%.
  7. 7. The substrate of claim 1, wherein the stacked structure (200) is located on a front side of the base layer (100), the graphene layer (300) is also located on a back side of the base layer (100).
  8. 8. The substrate according to claim 1, wherein the stacked structure (200) is located on the front and back sides of the base layer (100), the graphene layers (300) being located on the surfaces of two of the stacked structures (200) facing away from the base layer (100).
  9. 9. The substrate according to any one of claims 1, 7 or 8, wherein the graphene layer (300) has a thickness of 0.5-2 μm.
  10. 10. The substrate of claim 1, wherein the substrate is a package substrate for an LED chip.

Description

Substrate board Technical Field The application relates to the technical field of LEDs, in particular to a substrate. Background In the field of LED packaging, the substrate plays a vital role. The main current substrates are resin substrates, metal substrates and ceramic substrates, and the metal substrates are widely used because of their advantages in heat conduction, electrical insulation, mechanical workability and the like. The base layer of the metal substrate is usually mainly made of aluminum, copper and iron, but copper is high in cost and poor in iron stability, so that the aluminum-based metal substrate is most widely applied. With the continuous development of the LED technology, the requirement on the heat radiation performance of the substrate is higher and higher, the problems of poor heat radiation performance, heat accumulation and the like of the traditional metal substrate for LED packaging still exist, the accelerated light attenuation and the shortened service life are caused, and particularly, when a multi-chip array is packaged, the heat superposition effect is obvious, so that the problems of bonding layer fracture, interface stripping, substrate cracking or deformation and the like are caused. Disclosure of utility model In view of the above, embodiments of the present application are directed to providing a substrate to solve the problems of difficult heat dissipation and concentrated thermal stress of the substrate in the prior art. In one aspect, the application provides a substrate comprising a base layer, a stacked structure and a graphene layer, wherein the base layer is provided with a front surface and a back surface which are oppositely arranged, the stacked structure is at least positioned on the front surface of the base layer, and the graphene layer is at least positioned on the surface of the stacked structure, which is away from the base layer; The stacked structure includes at least two stress buffer layers, each having a coefficient of thermal expansion that is between that of the base layer and that of the graphene layer, and the closer to the base layer, the greater the coefficient of thermal expansion of the stress buffer layer. In some embodiments, the stress buffer layer comprises a stacked first stress buffer layer and at least one second stress buffer layer, the first stress buffer layer being closer to the base layer than the second stress buffer layer, the first stress buffer layer being of non-porous structure or having at least one first through-hole therein and at least one second through-hole therein; The aperture of the first through hole is larger than that of the second through hole, the porosity of the first stress buffer layer is smaller than that of the second stress buffer layer, and the closer to the second stress buffer layer of the base layer, the larger the aperture of the second through hole is, the smaller the porosity is. In some embodiments, at least a portion of the second through holes in adjacent two of the second stress buffer layers are in communication with each other, and/or at least a portion of the first through holes in the first stress buffer layers are in communication with at least a portion of the second through holes in adjacent second stress buffer layers. In some embodiments, the first through-hole is a constant diameter hole, or the aperture of the first through-hole gradually increases in a direction approaching the base layer, and the minimum aperture of the first through-hole is greater than or equal to 20% of the maximum aperture thereof, and The second through holes are equal-diameter holes, or the aperture of the second through holes is gradually increased along the direction close to the base layer, and the minimum aperture of the second through holes is more than or equal to 20% of the maximum aperture of the second through holes. In some embodiments, the base layer is made of aluminum, the second stress buffer layer has three layers, the first layer to the third layer are sequentially stacked on the surface of the first stress buffer layer facing away from the base layer, the thermal expansion coefficient of the first stress buffer layer is 16×10 -6/K～18×10-6/K, and the thermal expansion coefficients of the first layer to the third layer are 12×10 -6/K～14×10-6/K、9×10-6/K～10×10-6/K and 7×10 -6/K～8×10-6/K, respectively. In some embodiments, the second stress buffer layer has three layers, the first layer to the third layer are sequentially stacked on the surface of the first stress buffer layer, which is away from the base layer, the apertures of the first layer to the third layer are respectively 200nm to 500nm, 50nm to 200nm and 10nm to 50nm, and the porosities are respectively 10% -20%, 20% -30% and 30% -50%. In some embodiments, the stacked structure is located on a front side of the base layer, and the graphene layer is also located on a back side of the base layer. In some embodiments, the stacked structures