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CN-224205315-U - Anti-electromagnetic interference electronic chip high-density wiring structure

CN224205315UCN 224205315 UCN224205315 UCN 224205315UCN-224205315-U

Abstract

The utility model discloses an anti-electromagnetic interference high-density wiring structure of an electronic chip, and belongs to the field of electronic chips. The utility model provides an anti-electromagnetic interference's electronic chip high density wiring structure, includes circuit substrate, the surface of wire carrier plate is provided with expands space mechanism, the inside of wire carrier plate is provided with anti-electromagnetic interference mechanism, the surface of wire carrier plate and carrier plate body is provided with high-efficient heat dissipation mechanism. The utility model not only improves the performance and the power efficiency of the device when the wiring structure is used, but also reduces the size and the weight of the wiring structure, so that the first chip and the second chip can keep stable operation in a complex environment when the wiring structure is used, simultaneously, high-frequency noise is restrained, the occurrence of crosstalk phenomenon is reduced, and the adverse effect of overheating on the performance and the physical structure of the first chip and the second chip is prevented when the wiring structure is used, and meanwhile, the phenomenon that the device frequently fails due to overheating is avoided.

Inventors

  • HUANG JINHU

Assignees

  • 泉州亨鹭达电子科技有限公司

Dates

Publication Date
20260505
Application Date
20250715

Claims (8)

  1. 1. The high-density wiring structure of the electronic chip for resisting electromagnetic interference comprises a circuit substrate (1) and is characterized in that a wire carrier plate (101) is arranged above the circuit substrate (1), a carrier plate body (103) is arranged on the surface of the bottom position of the wire carrier plate (101), equidistant second metal ball pins (108) are arranged on the surface of the bottom position of the carrier plate body (103), the surface of the bottom position of the second metal ball pins (108) is contacted with the surface of the circuit substrate (1), a package plate (102) is arranged on the surface of the top position of the wire carrier plate (101), an expansion space mechanism (2) is arranged on the surface of the wire carrier plate (101), an electromagnetic interference resisting mechanism (3) is arranged inside the wire carrier plate (101), and an efficient heat dissipation mechanism (4) is arranged on the surface of the carrier plate body (103).
  2. 2. The high-density wiring structure of an electronic chip with electromagnetic interference resistance according to claim 1, wherein a first die (105) is disposed inside the package board (102), a second die (110) is disposed inside the package board (102), first metal ball pins (107) are mounted on surfaces at bottom positions of the first die (105) and the second die (110), the surfaces at the bottom positions of the first metal ball pins (107) are in contact with surfaces of a wire carrier board (101), the first die (105) and the second die (110) are connected with the wire carrier board (101) through the first metal ball pins (107), the wire carrier board (101) and the carrier board body (103) are connected with a circuit substrate (1) through the second metal ball pins (108), first chips (104) are mounted on surfaces at top positions of the second die (110), second chips (106) are mounted on surfaces at the top positions of the first die (105), the surfaces at the bottom positions of the wire carrier board (107) are in contact with surfaces of a wire carrier board (101), an intermediate layer (109) is disposed on the surfaces of the wire carrier board (101) and the intermediate layer (109) is connected with the surfaces of the second die carrier board (109), and external signals are connected to the wiring board (1) through the silicon interposer (109).
  3. 3. The high-density wiring structure of an electronic chip with electromagnetic interference resistance according to claim 1, wherein the expanding space mechanism (2) is composed of a first thin insulating medium layer (21), a first copper foil (22), a second thin insulating medium layer (23), a second copper foil (24), a blind hole (25) and a conductive path (26), the second copper foil (24) is mounted on the surface of the wire carrier plate (101), the second thin insulating medium layer (23) is mounted on the surface of the top of the second thin insulating medium layer (23), the first copper foil (22) is mounted on the surface of the top of the second thin insulating medium layer (23), and the first thin insulating medium layer (21) is mounted on the surface of the top of the first copper foil (22).
  4. 4. The high-density wiring structure of electronic chip with electromagnetic interference resistance according to claim 3, wherein the surfaces of the first thin insulating dielectric layer (21) and the second thin insulating dielectric layer (23) are provided with equidistant blind holes (25) by a laser drilling technology, and conductive paths (26) for conducting electricity are arranged inside the blind holes (25) by electroplating.
  5. 5. The high-density wiring structure of an anti-electromagnetic interference electronic chip according to claim 1, wherein the anti-electromagnetic interference mechanism (3) is composed of silicon carbide (31), a cavity (32), conductive adhesive (33) and a ternary alloy film (34), the cavity (32) is formed in the wire carrier plate (101), the silicon carbide (31) for improving the anti-interference capability of the first chip (104) and the second chip (106) is mounted on the inner wall of the cavity (32), and the conductive adhesive (33) for resisting electromagnetic interference of the first chip (104) and the second chip (106) is mounted on the surface of the bottom of the silicon carbide (31).
  6. 6. The high-density wiring structure of electronic chip for resisting electromagnetic interference according to claim 5, wherein a ternary alloy film (34) for improving the protection effect on the first chip (104) and the second chip (106) is mounted on the surface at the bottom position of the conductive adhesive (33), and the surface at the bottom position of the ternary alloy film (34) is fixed with the inner wall of the cavity (32).
  7. 7. The high-density wiring structure of an anti-electromagnetic interference electronic chip of claim 1, wherein the efficient heat dissipation mechanism (4) is composed of a heat dissipation fin (41), a mounting screw (42), a heat dissipation through hole (43) and a heat dissipation copper plate (44), the surfaces of two sides of the lead carrier plate (101) and the carrier plate body (103) are both provided with the heat dissipation fin (41) for heat dissipation, the surfaces of the heat dissipation fin (41) are both in threaded connection with the mounting screw (42), and one end of the mounting screw (42) penetrates through the heat dissipation fin (41) and is in threaded fastening with the surface of the lead carrier plate (101).
  8. 8. The high-density wiring structure of electronic chip with electromagnetic interference resistance as set forth in claim 1, wherein the inner walls of the wire carrier plate (101) are provided with heat dissipation copper plates (44) for heat conduction, the heat dissipation copper plates (44) and the inner walls of the wire carrier plate (101) are provided with equidistant heat dissipation through holes (43), and the heat dissipation through holes (43) are communicated with the inside of the wire carrier plate (101).

Description

Anti-electromagnetic interference electronic chip high-density wiring structure Technical Field The present utility model relates to the field of electronic chip technologies, and in particular, to an electromagnetic interference resistant high-density wiring structure for an electronic chip. Background The chip is also called microcircuit, microchip and integrated circuit, and is a silicon chip containing integrated circuit, the main purpose of chip wiring is to realize efficient signal transmission and connection so as to ensure the performance and function of the chip, the existing wiring structure has the defects that noise and interference in the wiring structure may cause signal distortion and the like, the problems may affect the performance, reliability and manufacturing cost of the chip, and in order to meet the market demand, an anti-electromagnetic interference electronic chip high-density wiring structure is required. Through searching, china patent No. 202420153687.1 discloses a chip high-density wiring packaging structure, which comprises a circuit substrate, an upper carrier plate, a plurality of groups of carrier plates and a plurality of groups of connecting plates, wherein the upper carrier plate is arranged above the circuit substrate, two adjacent groups of carrier plates are communicated through wire bonding, and the plurality of groups of carrier plates are connected with the upper end of the circuit substrate. The chip high-density wiring packaging structure in the patent has the defects that the anti-electromagnetic interference performance of the traditional wiring structure is not good enough when the wiring structure is used, so that the first chip and the second chip cannot keep stable operation in a complex environment when the wiring structure is used, high-frequency noise is increased, and the occurrence of crosstalk phenomenon is increased. Disclosure of utility model The utility model aims to solve the problems of insufficient wiring space, insufficient electromagnetic interference resistance and insufficient heat dissipation efficiency in the use of a wiring structure in the prior art, and provides an electromagnetic interference resistant high-density wiring structure of an electronic chip. In order to achieve the above purpose, the present utility model adopts the following technical scheme: The utility model provides an anti-electromagnetic interference's electronic chip high density wiring structure, includes circuit substrate, circuit substrate's top is provided with the wire carrier plate, the surface mounting of wire carrier plate bottom position department has the carrier plate body, equidistant second metal ball pin is all installed to the surface of carrier plate body bottom position department, the surface of second metal ball pin bottom position department contacts with circuit substrate's surface, the surface mounting of wire carrier plate top position department has the package plate, the surface of wire carrier plate is provided with expands space mechanism, the inside of wire carrier plate is provided with anti-electromagnetic interference mechanism, the surface of wire carrier plate and carrier plate body is provided with high-efficient heat dissipation mechanism. According to the preferred technical scheme, a first crystal grain is arranged in the packaging plate, a second crystal grain is arranged in the packaging plate, equidistant first metal ball pins are arranged on the surfaces of the bottom positions of the first crystal grain and the second crystal grain, the surfaces of the bottom positions of the first metal ball pins are in contact with the surfaces of the wire carrier plate, the first crystal grain and the second crystal grain are connected with the wire carrier plate through the first metal ball pins, the wire carrier plate is connected with the circuit substrate through the second metal ball pins, a first chip is arranged on the surface of the top position of the second crystal grain, a second chip is arranged on the surface of the top position of the first crystal grain, a silicon medium layer for improving signals is arranged on the central position of the surface of the wire carrier plate, the surfaces of the bottom positions of the first metal ball pins are in contact with the surfaces of the silicon medium layer, signals between the first crystal grain and the second crystal grain are connected with the wire carrier plate through the silicon medium layer, and external signals are connected with the circuit substrate through the silicon medium layer. As a preferable technical scheme of the application, the space expanding mechanism is composed of a first thin insulating medium layer, a first copper foil, a second thin insulating medium layer, a second copper foil, blind holes and conductive paths, wherein the second copper foil is arranged on the surface of the lead carrier plate, the second thin insulating medium layer is arranged on the