CN-224205519-U - 4T2FC ferroelectric memory cell and memory array

Abstract

The application provides a 4T2FC ferroelectric memory cell and a memory array, wherein the 4T2FC ferroelectric memory cell comprises a silicon substrate, a first memory transistor and a first control transistor, which are arranged on the silicon substrate, wherein a first active device area and a second active device area which are isolated from each other are arranged on the silicon substrate, the first memory transistor and the first control transistor are arranged on the first active device area, the drain electrode of the first memory transistor is electrically connected with the source electrode of the first control transistor, the second memory transistor and the second control transistor are arranged on the second active device area, the source electrode of the second memory transistor is electrically connected with the drain electrode of the second control transistor, and the first ferroelectric capacitor and the second ferroelectric capacitor are respectively arranged above grid stacking structures of the first memory transistor and the second memory transistor. The application realizes ferroelectric storage by adopting four transistors and two ferroelectric capacitors, improves the durability and improves the data retention and writing stability.

Inventors

• ZHU ZHILONG

Assignees

• 上海深明奥思半导体科技有限公司

Dates

Publication Date

20260505

Application Date

20250731

Claims (10)

1. 1. A 4T2FC ferroelectric memory cell comprising: A silicon substrate provided with a first active device region and a second active device region isolated from each other; The first storage transistor and the first control transistor are arranged on the first active device region, and the drain electrode of the first storage transistor is electrically connected with the source electrode of the first control transistor; The second storage transistor and the second control transistor are arranged on the second active device region, and the source electrode of the second storage transistor is electrically connected with the drain electrode of the second control transistor; the first ferroelectric capacitor and the second ferroelectric capacitor are respectively arranged above the grid electrode stacking structures of the first storage transistor and the second storage transistor.
2. 2. The 4T2FC ferroelectric memory cell of claim 1, wherein each of said first memory transistor, said second memory transistor, said first control transistor, said second control transistor, comprises: the grid electrode stacking structure is arranged on the active device region; The source diffusion region is arranged on the active device region and is positioned on one side of the grid stacking structure; the drain diffusion region is arranged on the active device region and is positioned on the other side of the grid stacking structure; The first ferroelectric capacitor is arranged between a first plate line and the grid stacking structure; the second ferroelectric capacitor is arranged between a second plate line and the grid stacking structure.
3. 3. The 4T2FC ferroelectric memory cell of claim 2, further comprising: a storage gate line connected to gate stack structures of the first storage transistor and the second storage transistor, respectively; A control line electrically connected to the gate stack structures of the first and second control transistors; a source line electrically connected to a source diffusion region of the first memory transistor and/or the second memory transistor; and a bit line electrically connected with the drain diffusion region of the first control transistor and/or the second control transistor.
4. 4. The 4T2FC ferroelectric memory cell of claim 3, further comprising: a first storage gate contact hole and a second storage gate contact hole respectively connected to gate stack structures of the first storage transistor and the second storage transistor; A first storage gate contact landing pad, a second storage gate contact landing pad connected to gate stack structures of the first storage transistor and the second storage transistor, respectively; The storage gate line is coupled to the first storage transistor gate and the second storage transistor gate through the first storage gate contact landing pad and the second storage gate contact landing pad.
5. 5. The 4T2FC ferroelectric memory cell of claim 3, further comprising a first via landing pad, a second via Kong Zhaoliu pad, said first via landing pad connected to said storage gate line and a bottom electrode of said first ferroelectric capacitor, respectively, said second via Kong Zhaoliu pad connected to said storage gate line and a bottom electrode of said second ferroelectric capacitor, respectively.
6. 6. The 4T2FC ferroelectric memory cell of claim 2, wherein said gate stack comprises a gate oxide layer, a high dielectric constant dielectric layer and a TiN gate electrode, said gate oxide layer being disposed on said active device region, said high dielectric constant dielectric layer and TiN gate electrode being sequentially stacked and disposed on said gate oxide layer.
7. 7. The 4T2FC ferroelectric memory cell of claim 3 further comprising an interlayer dielectric disposed over the source diffusion region and the drain diffusion region, wherein the interlayer dielectric defines a plurality of contact holes filled with a conductive metal, and wherein the source line and the bit line are electrically connected to the source diffusion region and the drain diffusion region through the conductive metal in the contact holes, respectively.
8. 8. The 4T2FC ferroelectric memory cell of claim 1 wherein each of the first ferroelectric capacitor, the second ferroelectric capacitor comprises a TiN bottom electrode, a ferroelectric layer, and a TiN top electrode.
9. 9. The 4T2FC ferroelectric memory cell of claim 1, wherein the silicon substrate is further provided with shallow trench isolation regions surrounding the first and second active device regions, respectively, and the shallow trench isolation regions are filled with oxide.
10. 10. A memory array comprising a plurality of 4T2FC ferroelectric memory cells according to any one of claims 1-9.

Description

4T2FC ferroelectric memory cell and memory array Technical Field The application relates to the technical field of ferroelectric memories, in particular to a 4T2FC ferroelectric memory cell and a memory array. Background With the development of Artificial Intelligence (AI) and neuromorphic computing, there is a push for a need for memory systems that are high-speed, high-density, and support non-volatile in-memory computing (IMC). in-Memory-storage (CiM) is a framework that integrates computing functions directly into a storage array, enabling reduced data handling power consumption. The ferroelectric Memory (frim, ferroelectric RAM) is used as a new Non-Volatile Memory (NVM) capable of capturing and storing critical data immediately upon power interruption, and is very suitable for mission critical data recording applications, and the ferroelectric Memory is designed to be low-power consumption and miniaturized, and can provide instant Non-Volatile and almost infinite endurance without affecting speed or energy efficiency. Existing ferroelectric memories mainly employ ferroelectric field effect transistors (fefets), which can have stable multilevel states, and suitable sensing circuits can be designed to sense current or threshold voltage to distinguish AI applications (memory computation) of multiple states. However, fefets are prone to problems such as degradation in durability, degradation in data retention capability, and increased sensitivity to read and write disturbances in high frequency operation due to polarization shielding effects and ferroelectric domain dynamics limitations. Disclosure of Invention In order to solve the defects in the prior art, the application aims to provide a 4T2FC ferroelectric memory cell and a memory array, which realize ferroelectric memory by adopting four transistors and two ferroelectric capacitors and improve the data holding capacity and the read-write stability. To achieve the above object, the present application provides a 4T2FC ferroelectric memory cell comprising: A silicon substrate provided with a first active device region and a second active device region isolated from each other; The first storage transistor and the first control transistor are arranged on the first active device region, and the drain electrode of the first storage transistor is electrically connected with the source electrode of the first control transistor; The second storage transistor and the second control transistor are arranged on the second active device region, and the source electrode of the second storage transistor is electrically connected with the drain electrode of the second control transistor; the first ferroelectric capacitor and the second ferroelectric capacitor are respectively arranged above the grid electrode stacking structures of the first storage transistor and the second storage transistor. Further, each of the first memory transistor, the second memory transistor, the first control transistor, the second control transistor, includes: the grid electrode stacking structure is arranged on the active device region; The source diffusion region is arranged on the active device region and is positioned on one side of the grid stacking structure; the drain diffusion region is arranged on the active device region and is positioned on the other side of the grid stacking structure; The first ferroelectric capacitor is arranged between a first plate line and the grid stacking structure; the second ferroelectric capacitor is arranged between a second plate line and the grid stacking structure. Further, the method further comprises the following steps: a storage gate line connected to gate stack structures of the first storage transistor and the second storage transistor, respectively; A control line electrically connected to the gate stack structures of the first and second control transistors; a source line electrically connected to a source diffusion region of the first memory transistor and/or the second memory transistor; and a bit line electrically connected with the drain diffusion region of the first control transistor and/or the second control transistor. Further, the method further comprises the following steps: a first storage gate contact hole and a second storage gate contact hole respectively connected to gate stack structures of the first storage transistor and the second storage transistor; A first storage gate contact landing pad, a second storage gate contact landing pad connected to gate stack structures of the first storage transistor and the second storage transistor, respectively; The storage gate line is coupled to the first storage transistor gate and the second storage transistor gate through the first storage gate contact landing pad and the second storage gate contact landing pad. Further, the semiconductor device further comprises a first through hole landing pad and a second through hole Kong Zhaoliu pad, wherein the first through hole landing p