CN-224205643-U - Electronic chip

CN224205643UCN 224205643 UCN224205643 UCN 224205643UCN-224205643-U

Abstract

The present disclosure relates to electronic chips. There is provided an electronic chip of CSP type having electromagnetic shielding, comprising an insulating substrate having a resistivity higher than 1kΩ.cm and comprising a lower surface, side surfaces and an upper surface, an interconnect structure covering the upper surface of the substrate, the interconnect structure comprising an insulating layer in which conductive tracks are formed, the connection pads being arranged on the interconnect structure, the conductive tracks being arranged to be exposed on at least one of one or more sides of the interconnect structure, a resin covering the interconnect structure and leaving a passage to a portion of the connection pads, and a conductive coating covering and contacting the side surfaces and lower surface of the substrate of the chip and the sides of the interconnect structure to connect the conductive tracks to the conductive coating on at least one of the sides of the interconnect structure.

Inventors

L. Falud
CHARI SUJAI

Assignees

意法半导体国际公司

Dates

Publication Date: 20260505
Application Date: 20250423
Priority Date: 20240423

Claims (6)

1. An electronic chip of CSP type with electromagnetic shielding, comprising: -an insulating substrate having a resistivity higher than 1kΩ.cm and comprising a lower surface, a side surface and an upper surface, an active portion of an electronic chip being formed on the substrate; -an interconnect structure covering the upper surface of the substrate, the interconnect structure comprising an insulating layer having conductive tracks formed therein, the connection pads being arranged on the interconnect structure, the conductive tracks being arranged to be exposed on at least one of one or more sides of the interconnect structure; A resin covering the interconnect structure and leaving a passage to a portion of the connection pad, and -A conductive coating covering and contacting the side and lower surfaces of the substrate of the chip and the sides of the interconnect structure to connect the conductive tracks to the conductive coating on at least one of the sides of the interconnect structure.
2. The electronic chip of claim 1, wherein the conductive track has a thickness in the range of from 2 to 12 μm.
3. The electronic chip of claim 1, wherein the width of the conductive track is greater than 10 μm.
4. The electronic chip of claim 1, wherein the conductive coating is made of silver.
5. The electronic chip of claim 1, wherein the conductive tracks exposed on the sides of the interconnect structure have comb-shaped ends.
6. The electronic chip of claim 1, wherein the conductive tracks are exposed on two opposite sides of the interconnect structure.

Description

Electronic chip Cross-reference to related application(s) The present application claims the benefit of priority from French patent application No. 2404174 entitled "Proc de fabric d' une puce e lectronique ayant un blindage e lectromagn e tique," filed on month 23 of 2024, which is hereby incorporated by reference to the maximum extent allowed by law. Technical Field The present disclosure relates to the field of CSP ("chip-level package") types or WLCSP ("wafer-level package") types of chips. And more particularly to a method of manufacturing an electronic chip with electromagnetic shielding. Background The electronic chip comprises a substrate in or on which electronic circuits have been fabricated. The substrate is covered with connection areas to allow the chip to be assembled with, for example, a printed circuit board. The chip may be subject to electromagnetic interference (EMI) that interferes with its operation or may even cause significant damage, and/or such electromagnetic interference may be generated. In order to protect the chip from unwanted electromagnetic radiation, a mold (molding) is typically formed around the chip at the component level, and an electromagnetic shield is formed around the mold. Alternatively, a second molding may be formed on the electromagnetic shield. Grounding of the electromagnetic shield may be achieved by means of vias and/or laminates and may also be used to add antennas. For manufacturing electronic chips, low temperature co-fired ceramics (LTCCs) may be used, which include multiple dielectric layers, conductive material (e.g., screen printed), and holes for interconnecting the different layers. Because of the use of holes/vias, the shield is easy to manufacture. Such chips include many interconnect layers and elements and are therefore complex to manufacture and/or increase the size of the final chip. Disclosure of utility model There is a need to at least partially improve certain aspects of known methods of manufacturing electronic chips that include electromagnetic shielding. This object is achieved by a method of manufacturing an electronic chip with electromagnetic shielding, comprising the steps of: i) Providing an electronic chip comprising: -an insulating substrate comprising a lower surface, a side surface and an upper surface; -an interconnect structure covering the upper surface of the substrate, the interconnect structure comprising an insulating layer having conductive tracks formed therein, the pads being arranged on the interconnect structure, the conductive tracks being arranged to be exposed on at least one of the sides of the interconnect structure; -a resin covering the upper surface of the interconnect structure and partially coating the connection pads to enable connection of the connection pads to external components; ii) forming a conductive coating on the side surfaces and on the lower surface of the substrate and on the sides of the interconnect structure, whereby the conductive coating is connected to the conductive tracks on at least one of the sides of the interconnect structure. According to a specific embodiment, step ii) is performed by spraying a solution or by ink-jetting. According to a specific embodiment, the solution or ink comprises silver nanoparticles. According to a specific embodiment, the electronic chip provided at step i) is obtained according to the following steps: Providing a substrate covered by an interconnect structure, the connection pads being arranged on the interconnect structure, the conductive tracks being arranged to be exposed on at least one of the sides of the interconnect structure, Depositing a resin on the interconnect structure and on the connection pads, Thinning the resin to leave a channel to a portion of the connection pad, Possibly thinning the substrate and/or covering the back side of the chip with an additional resin layer, -Dicing the substrate into different chips. The object is also achieved by an electronic chip comprising: -an insulating substrate comprising a lower surface, a side surface and an upper surface; -an interconnect structure covering the upper surface of the substrate, the interconnect structure comprising an insulating layer having conductive tracks formed therein, the connection pads being arranged on the interconnect structure, the conductive tracks being arranged to be exposed on at least one of the sides of the interconnect structure; -a resin covering the interconnect structure and leaving a channel to a portion of the connection pad; -a conductive coating covering and contacting the side and lower surfaces of the substrate of the chip and the sides of the interconnect structure to connect the conductive tracks to the conductive coating on at least one of the sides of the interconnect structure. According to a specific embodiment, the thickness of the conductive track is in the range from 2 to 12 μm. According to a specific embodiment, the width of the conductive tr