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CN-224205661-U - Chip packaging structure and electronic equipment

CN224205661UCN 224205661 UCN224205661 UCN 224205661UCN-224205661-U

Abstract

The application discloses a chip packaging structure and electronic equipment, the chip packaging structure comprises a plurality of first packaging bodies, a second substrate and first reinforcing ribs, the first packaging bodies comprise first bare chips, first substrates and first packaging layers, the first bare chips are welded on the first substrates and are electrically connected with the first substrates, the first packaging layers are positioned on the first substrates, the first packaging layers wrap the side surfaces of the first bare chips, the plurality of first packaging bodies are welded on the second substrates, the first substrates are electrically connected with the second substrates, the first substrates are at least used for realizing the electrical connection between the first bare chips and the second substrates, the second substrates are at least used for realizing the electrical connection between the first packaging bodies and other devices, the first reinforcing ribs are fixed on the second substrates, and the first reinforcing ribs are positioned between the adjacent first packaging bodies, so that the warping of the second substrates and the chip packaging structure is smaller.

Inventors

  • LI JUNFENG
  • HUANG CHENJUN
  • ZENG WEI
  • WANG QIANG

Assignees

  • 飞腾信息技术有限公司

Dates

Publication Date
20260505
Application Date
20250428

Claims (10)

  1. 1. A chip package structure, comprising: A plurality of first packages; the first package includes a first die, a first substrate, and a first encapsulation layer; the first bare chip is welded on the first substrate and is electrically connected with the first substrate; the first packaging layer is positioned on the first substrate, and the first packaging layer wraps the side face of the first bare chip; The first substrate is at least used for realizing the electric connection between the first bare chip and the second substrate, and the second substrate is at least used for realizing the interconnection between the first packages and the electric connection between the first packages and other devices; The first reinforcing ribs are fixed on the second substrate and are positioned between the adjacent first packaging bodies.
  2. 2. The chip package structure according to claim 1, wherein the first package comprises a first package and/or a second package; The first package includes one of the first die and one of the first substrate; the second package body comprises a plurality of first bare chips, a first substrate and second reinforcing ribs, wherein the first substrate in the second package body is also used for realizing interconnection between the first bare chips, the second reinforcing ribs are fixed on the first substrate, and the second reinforcing ribs are positioned between the adjacent first bare chips.
  3. 3. The chip package structure of claim 2, wherein the second package further comprises a third stiffener, the third stiffener being affixed to the first substrate and the third stiffener being disposed around all of the first dies of the second package.
  4. 4. The chip package structure according to any one of claims 1 to 3, further comprising a fourth stiffener, wherein the fourth stiffener is fixed on the second substrate, and the fourth stiffener is disposed around the plurality of first packages.
  5. 5. The chip packaging structure according to claim 4, further comprising a packaging cover plate, wherein the packaging cover plate is fixedly connected with one side, away from the second substrate, of the fourth reinforcing rib, or the packaging cover plate and the fourth reinforcing rib are integrally formed, an accommodating space is formed by the packaging cover plate, the fourth reinforcing rib and the second substrate, and the plurality of first packaging bodies are located in the accommodating space.
  6. 6. The chip package structure of claim 1, further comprising a second die and a fifth stiffener; the second bare chip is welded on the second substrate and is electrically connected with the second substrate, the fifth reinforcing rib is positioned on the second substrate, and the fifth reinforcing rib is positioned between the first packaging body and the second bare chip.
  7. 7. The chip package structure of claim 1, wherein the materials of the first substrate and the second substrate each comprise an organic material, and the material of the first stiffener comprises an inert metal material.
  8. 8. The chip package structure according to claim 1, wherein a side of the first bare chip facing the first substrate is provided with a plurality of first bonding pads, a side of the first substrate facing away from the first bare chip is provided with a plurality of second bonding pads, a side of the second substrate facing away from the first package body is provided with a plurality of third bonding pads, a spacing between the second bonding pads is larger than a spacing between the first bonding pads, and/or a spacing between the third bonding pads is larger than a spacing between the second bonding pads.
  9. 9. The chip package structure according to claim 1, further comprising a first passive device and/or a second passive device, wherein the first passive device is disposed on the first substrate and the first passive device is electrically connected to the first substrate, and the second passive device is disposed on the second substrate and the second passive device is electrically connected to the second substrate.
  10. 10. An electronic device comprising the chip package structure of any one of claims 1-9.

Description

Chip packaging structure and electronic equipment Technical Field The present application relates to the field of chip technologies, and in particular, to a chip packaging structure and an electronic device. Background Current chip packaging structures include a package substrate and a Die (Die) soldered to the package substrate. Wherein the die may be electrically connected to other devices such as a printed circuit board through signal lines and pads on the package substrate. However, as the integration level of the chip is higher, the number of the bare chips soldered on the single package substrate is higher, so that the package substrate is warped more and more, and further, the chip package structure is warped more and more. Disclosure of utility model The application discloses a chip packaging structure and electronic equipment, which are used for solving the problem that the warpage of the chip packaging structure is larger and larger along with the higher and higher integration level of a chip. In a first aspect, the application discloses a chip packaging structure, which comprises a plurality of first packaging bodies, wherein each first packaging body comprises a first bare chip, a first substrate and a first packaging layer, the first bare chip is welded on the first substrate and is electrically connected with the first substrate, the first packaging layer is positioned on the first substrate and wraps the side face of the first bare chip, the second substrate is welded on the second substrate and is electrically connected with the second substrate, the first substrate is at least used for realizing the interconnection between the first bare chips and the second substrate and the electrical connection between the first packaging body and other devices, the first reinforcing ribs are fixed on the second substrate and are positioned between the adjacent first packaging bodies. In this way, first, since the plurality of first packages can be soldered on the second substrate, the difference in area of the first substrate and the die is smaller compared to the difference in area of the second substrate and the die, so that the warpage of the first substrate after soldering the die can be made smaller, and further, the warpage of the second substrate and the chip package structure can be made smaller. Second, warpage of the second substrate and the chip package structure can be further reduced by the first stiffener fixed on the second substrate and located between the adjacent first packages. And thirdly, welding the first bare chip on the first substrate and forming a first packaging layer wrapping the side face of the first bare chip on the first substrate to form a first packaging body, and welding a plurality of first packaging bodies on the second substrate, wherein the welding risk probability of short circuit and the like between the first packaging bodies and the second substrate can be reduced by enabling the space between bonding pads on the first substrate to be larger than that between bonding pads on the first bare chip, and further the welding risk probability of a chip packaging structure can be further reduced. In addition, even if the welding problems such as short circuit and the like occur between a certain first packaging body and a second substrate, the welding between other first packaging bodies and the second substrate is not influenced, and the yield and the stability of the chip packaging structure can be improved. In some embodiments of the present application, the first package includes a first package and/or a second package, the first package includes one first die and one first substrate, the second package includes a plurality of first dies, one first substrate and a second stiffener, the first substrate in the second package is further used for realizing interconnection between the first dies, the second stiffener is fixed on the first substrate, and the second stiffener is located between the adjacent first dies. In this way, not only the integration level of the chip package structure can be improved, but also warpage of the first substrate having a plurality of first dies and the chip package structure can be reduced by the second stiffener between the adjacent first dies. In some embodiments of the present application, the second package further includes a third stiffener, the third stiffener is fixed on the first substrate, and the third stiffener is disposed around all of the first dies of the second package. In this way, warpage of the first substrate and the chip package structure can be further reduced by the third stiffener surrounding all of the first die. In some embodiments of the present application, the chip package structure further includes a fourth stiffener, where the fourth stiffener is fixed on the second substrate, and the fourth stiffener is disposed around the plurality of first packages. In this way, warpage of the second substrate and the ch