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CN-224216747-U - Packaging structure for evaluating silicon optical chip

CN224216747UCN 224216747 UCN224216747 UCN 224216747UCN-224216747-U

Abstract

The application relates to the technical field of chip packaging, in particular to a packaging structure for evaluating a silicon optical chip, which comprises a circuit board and a chip carrier, wherein the circuit board is provided with a hollowed-out slot, the chip carrier is detachably connected with the circuit board, a boss which is inserted into the hollowed-out slot along the direction perpendicular to the circuit board is arranged on the chip carrier, the boss is provided with a bearing surface parallel to the circuit board, and the bearing surface is provided with the silicon optical chip which is electrically connected with the circuit board. The embodiment of the application not only can eliminate the adverse effect of the warpage of the circuit board on the silicon optical chip, but also can repeatedly use the circuit board, thereby effectively reducing the test cost.

Inventors

  • XU GUANGYING
  • HU ZHIPENG

Assignees

  • 北京光联芯科智能科技有限公司

Dates

Publication Date
20260508
Application Date
20250520

Claims (10)

  1. 1. A packaging structure for evaluating a silicon optical chip is characterized by comprising a circuit board (100) and a chip carrier (101), wherein a hollowed-out slot (103) is formed in the circuit board (100), the chip carrier (101) is detachably connected with the circuit board (100), a boss (104) which is inserted into the hollowed-out slot (103) along the direction perpendicular to the circuit board (100) is arranged on the chip carrier (101), the boss (104) is provided with a bearing surface (105) parallel to the circuit board (100), and the bearing surface (105) is provided with a silicon optical chip (102) which is electrically connected with the circuit board (100).
  2. 2. The packaging structure for evaluating the silicon optical chip according to claim 1, wherein the chip carrier (101) is provided with a carrier main body (106), the carrier main body (106) is positioned on one side of the circuit board (100) away from the silicon optical chip (102), the carrier main body (106) is provided with a contact surface (107) attached to the circuit board (100), the carrier main body (106) is provided with a connecting part (108), the circuit board (100) is provided with a locking part (109), and the locking part (109) is connected with the connecting part (108) so that the contact surface (107) is abutted against the circuit board (100).
  3. 3. The packaging structure for evaluating the silicon optical chip according to claim 2, wherein the circuit board (100) is provided with a positioning hole, the carrier body (106) is provided with a positioning structural member (110), and the positioning structural member (110) is inserted into the positioning hole in a matching manner along a direction perpendicular to the circuit board (100).
  4. 4. The packaging structure for evaluating a silicon optical chip according to claim 1, wherein an electrical chip (111) is attached to the carrying surface (105) at a position close to the silicon optical chip (102), and the electrical chip (111) is electrically connected to the circuit board (100) and the silicon optical chip (102), respectively.
  5. 5. The package structure for silicon photonics chip evaluation of claim 4 wherein the chip carrier (101) comprises a metal heat sink structure (112), the metal heat sink structure (112) being for dissipating heat from the electrical chip (111) and the silicon photonics chip (102).
  6. 6. The packaging structure for evaluating the silicon optical chip according to claim 5, wherein a mounting groove (113) is formed in one side, away from the circuit board (100), of the metal heat dissipation structure (112), the mounting groove (113) is provided with a mounting surface (114) close to the bearing surface (105), a thermoelectric cooler (115) is attached to the mounting surface (114), and projection of the thermoelectric cooler (115) on the circuit board (100) covers projection of the bearing surface (105) on the circuit board (100).
  7. 7. The packaging structure for evaluating the silicon optical chip according to any one of claims 1 to 6, wherein the bearing surface (105) is provided with an optical fiber array (116) in a pasting manner at a position close to the silicon optical chip (102), one side of the silicon optical chip (102) close to the optical fiber array (116) is provided with a plurality of waveguides (117), and the plurality of waveguides (117) are respectively in one-to-one correspondence with a plurality of light outlet positions of the optical fiber array (116).
  8. 8. The packaging structure for evaluating a silicon optical chip according to any one of claims 1 to 6, wherein a ceramic carrier is provided on a side of the silicon optical chip (102) facing away from the carrying surface (105), and a temperature detection unit (119) electrically connected to the circuit board (100) is provided on the ceramic carrier.
  9. 9. The packaging structure for evaluating a silicon optical chip according to any one of claims 1 to 6, further comprising a protective cover (120), wherein the protective cover (120) is fastened on the circuit board (100) to form a containing cavity, and the bearing surface (105) is located in the containing cavity.
  10. 10. The packaging structure for silicon photonics chip evaluation of any of claims 1-6 wherein the bearing surface (105) is flush with a surface of the circuit board (100) on a side proximate to the silicon photochip (102).

Description

Packaging structure for evaluating silicon optical chip Technical Field The application relates to the technical field of chip packaging, in particular to a packaging structure for evaluating a silicon optical chip. Background With the rapid development of the silicon optical chip technology, the application field of the silicon optical chip has been expanded from traditional optical communication to a plurality of emerging fields such as quantum computing, 6G communication, laser radar, biological sensing, optical interconnection and the like, and the silicon optical chip has wide market potential. As a core driving force in the fields of optical communication, data centers and artificial intelligence, the development speed of silicon optical chips puts higher demands on research and development and iteration efficiency. After chip streaming is completed, it becomes critical to evaluate chip performance quickly and comprehensively. In order to obtain detailed and accurate test data, a specific Chip On Board (COB) structure is designed for different chips to ensure accurate evaluation of chip performance indexes. In the conventional packaging structure, the chip is directly mounted on the circuit board, however, the circuit board is easy to generate warping phenomenon after undergoing a reflow soldering process, and for a silicon optical chip which needs to be optically coupled with the optical fiber array in a micron-scale precision, the stability and the accuracy of a coupling interface are seriously affected by the warping. Furthermore, the repairing difficulty is high, and in view of a certain failure rate in the coupling process of the silicon optical chip and the optical fiber array, the integrated COB packaging mode is difficult to repair when coupling failure occurs, and the whole PCB and components thereof are scrapped, so that the testing cost is increased and the overall economic benefit is reduced. Disclosure of utility model The application aims to provide a packaging structure for evaluating a silicon optical chip, which not only can eliminate the adverse effect of the warpage of a circuit board on the silicon optical chip, but also can repeatedly use the circuit board, thereby effectively reducing the test cost. Embodiments of the present application are implemented as follows: The embodiment of the application provides a packaging structure for evaluating a silicon optical chip, which comprises a circuit board and a chip carrier, wherein the circuit board is provided with a hollowed-out slot, the chip carrier is detachably connected with the circuit board, a boss which is inserted into the hollowed-out slot along the direction vertical to the circuit board is arranged on the chip carrier, the boss is provided with a bearing surface parallel to the circuit board, and the bearing surface is provided with the silicon optical chip which is electrically connected with the circuit board in a pasting mode. As an optional implementation mode, the chip carrier is provided with a carrier main body, the carrier main body is positioned on one side, away from the silicon optical chip, of the circuit board, the carrier main body is provided with a contact surface attached to the circuit board, a connecting part is arranged on the carrier main body, and a locking piece is arranged on the circuit board and connected with the connecting part so as to enable the contact surface to be abutted against the circuit board. As an alternative implementation mode, the circuit board is provided with a positioning hole, the carrier body is provided with a positioning structural member, and the positioning structural member is inserted into the positioning hole in a matched manner along the direction perpendicular to the circuit board. As an alternative embodiment, an electrical chip is attached to the carrying surface at a position close to the silicon optical chip, and the electrical chip is electrically connected with the circuit board and the silicon optical chip respectively. As an alternative embodiment, the chip carrier includes a metal heat dissipation structure for dissipating heat from the electrical chip and the silicon photonics chip. As an alternative implementation mode, one side, away from the circuit board, of the metal heat dissipation structure is provided with a mounting groove, the mounting groove is provided with a mounting surface close to the bearing surface, a thermoelectric cooler is attached to the mounting surface, and projection of the thermoelectric cooler on the circuit board covers projection of the bearing surface on the circuit board. As an optional implementation mode, the bearing surface is stuck with an optical fiber array at a position close to the silicon optical chip, one side of the silicon optical chip close to the optical fiber array is provided with a plurality of waveguides, and the plurality of waveguides are respectively in one-to-one correspondence with the plurality of lig