CN-224216972-U - Array substrate, display panel and display device

CN224216972UCN 224216972 UCN224216972 UCN 224216972UCN-224216972-U

Abstract

The embodiment of the disclosure provides an array substrate, a display panel and a display device. The display technology field is used for reducing the risk of short circuit between the data signal line and the first conductive layer. The array substrate comprises a substrate and a first conductive layer, a first insulating layer, a semiconductor layer and a second conductive layer which are stacked along a direction away from the substrate. The semiconductor layer comprises a semiconductor pattern and a plurality of auxiliary patterns, wherein the semiconductor pattern is arranged at intervals with at least one auxiliary pattern, and the semiconductor pattern comprises an active layer of a transistor. The second conductive layer comprises a data signal line, the orthographic projection of the data signal line on the substrate and the orthographic projection of the side wall of the first conductive layer on the substrate are provided with N first areas which are overlapped with each other, the orthographic projection of the auxiliary patterns on the substrate covers M first areas, M is more than or equal to 2 and less than or equal to N, and M and N are positive integers. The array substrate is used for preparing the display device.

Inventors

LIU YAN
ZHU YUANYUAN
PENG YUANYUAN
CHEN WEI
WANG XIAOYUAN
GUO JIANDONG
PU XUN
CHEN JUNMING
WAN BIN
GUO HUI
WU ZHONGSHAN
YANG GUODONG

Assignees

重庆京东方光电科技有限公司
京东方科技集团股份有限公司
北京京东方技术开发有限公司

Dates

Publication Date: 20260508
Application Date: 20250430

Claims (20)

1. An array substrate, characterized by comprising: A substrate, and a first conductive layer, a first insulating layer, a semiconductor layer, and a second conductive layer which are stacked in a direction away from the substrate, The semiconductor layer comprises a semiconductor pattern and a plurality of auxiliary patterns, the semiconductor pattern and at least one auxiliary pattern are arranged at intervals, the semiconductor pattern comprises an active layer of a transistor, the second conductive layer comprises a data signal line, the orthographic projection of the data signal line on the substrate and the orthographic projection of the side wall of the first conductive layer on the substrate are provided with N first areas which are overlapped mutually, the orthographic projection of the plurality of auxiliary patterns on the substrate covers M first areas, and M is more than or equal to 2 and less than or equal to N, and M and N are positive integers.
2. The array substrate of claim 1, wherein, The first conductive layer comprises a plurality of grid lines, the grid lines extend along a first direction and are arranged at intervals along a second direction, and the first direction intersects with the second direction; The data signal line comprises a first main body part extending along the second direction and a source electrode part positioned at one side of the first main body part, and at least part of the orthographic projection of the source electrode part on the substrate is positioned in the range of the orthographic projection of the grid line on the substrate; The orthographic projections of the side walls of the first main body part and the grid lines on the substrate in the first areas are overlapped with each other to form a first subarea; The plurality of auxiliary patterns comprise first auxiliary patterns, the first auxiliary patterns and the semiconductor patterns are arranged along the first direction, and orthographic projection of the first auxiliary patterns on the substrate covers the first sub-region.
3. The array substrate of claim 2, wherein, An orthographic projection of one first auxiliary pattern on the substrate covers one first sub-region, and a space is arranged between two adjacent first auxiliary patterns.
4. The array substrate of claim 2, wherein, And the orthographic projection of one first auxiliary pattern on the substrate covers the two first sub-areas where orthographic projections of the side wall of the first main body part and the same grid line are overlapped on the substrate.
5. The array substrate according to any one of claims 2 to 4, wherein, And the orthographic projection of the source electrode part on the substrate is positioned in the orthographic projection range of the grid line on the substrate.
6. The array substrate according to any one of claims 2 to 4, wherein, The orthographic projection of one end of the source electrode part on the substrate is positioned outside the orthographic projection of the grid line on the substrate and is connected with the first main body part; The orthographic projections of the side walls of the source electrode part and the grid line on the substrate in the first areas are overlapped with each other to form a second subarea; The plurality of auxiliary patterns comprises a second auxiliary pattern, and the orthographic projection of the second auxiliary pattern on the substrate covers the second sub-region.
7. The array substrate of claim 6, wherein, The second auxiliary pattern is connected with the semiconductor pattern into an integral structure.
8. The array substrate of claim 6, wherein, The second auxiliary pattern is connected with the first auxiliary pattern nearest to the second auxiliary pattern as a unitary structure.
9. The array substrate according to any one of claims 2 to 4, wherein, And the size of the part, overlapped with the orthographic projection of the data signal line on the substrate, of the grid line on the substrate is 3.5-7 mu m along the second direction.
10. The array substrate of claim 1, wherein, The first conductive layer comprises a plurality of grid lines, the grid lines extend along a first direction and are arranged at intervals along a second direction, and the first direction intersects with the second direction; The data signal line extends along the second direction, and the orthographic projection of the data signal line on the substrate and the orthographic projection of the grid line on the substrate are overlapped to form a source electrode part; in the first areas, the area where orthographic projections of the side walls of the data signal lines and the grid lines on the substrate overlap each other is a third subarea; The plurality of auxiliary patterns comprise a third auxiliary pattern, the third auxiliary pattern and the semiconductor pattern are arranged along the second direction, and orthographic projection of the third auxiliary pattern on the substrate covers the third sub-region.
11. The array substrate of claim 10, wherein, The semiconductor pattern is spaced apart from at least one of the third auxiliary patterns.
12. The array substrate of claim 10, wherein, The semiconductor pattern and at least one of the third auxiliary patterns are connected as an integral structure.
13. The array substrate of claim 1, the array substrate is characterized by further comprising: the first electrode is arranged on one side of the second conductive layer away from the substrate; the second electrode is arranged on one side of the first electrode away from the substrate; The second conductive layer further comprises a drain electrode part which is respectively and electrically connected with the semiconductor pattern and the first electrode, and the first conductive layer further comprises a plurality of first voltage signal lines which are electrically connected with the second electrode; The area where orthographic projections of the side walls of the data signal lines and the first voltage signal lines on the substrate overlap with each other is a fourth subarea in the plurality of first areas; The plurality of auxiliary patterns comprises a fourth auxiliary pattern, and orthographic projection of the fourth auxiliary pattern on the substrate covers the fourth sub-region.
14. The array substrate of claim 13, wherein, One of the fourth auxiliary patterns covers the two fourth sub-areas where the orthographic projections of the side walls of the data signal line and the same first voltage signal line on the substrate coincide.
15. The array substrate of claim 13 or 14, wherein, The fourth auxiliary pattern is spaced apart from the adjacent auxiliary pattern and spaced apart from the semiconductor pattern.
16. The array substrate of claim 13 or 14, wherein, The fourth auxiliary pattern is connected with one auxiliary pattern nearest to the fourth auxiliary pattern into an integral structure.
17. The array substrate of claim 1, wherein, The interval between the orthographic projection boundary of the auxiliary pattern on the substrate and the boundary of the first area covered by the auxiliary pattern is 1-5 mu m.
18. The array substrate of claim 17, wherein, At least two boundaries of the orthographic projection of the auxiliary pattern on the substrate are not equal to the interval between the boundaries of the first area covered by the auxiliary pattern.
19. The array substrate of claim 1, wherein, The shape of the orthographic projection of at least one auxiliary pattern on the substrate is the same as that of the orthographic projection of the target section of the data signal line on the substrate, and the orthographic projection of the target section on the substrate is positioned in the orthographic projection range of the auxiliary pattern on the substrate.
20. The array substrate of claim 1, wherein, The second conductive layer further includes a drain electrode portion electrically connected to the semiconductor pattern; the orthographic projection of the drain electrode part on the substrate and the orthographic projection of the side wall of the first conductive layer on the substrate are overlapped to form a second area; An orthographic projection of the semiconductor pattern on the substrate covers the second region.

Description

Array substrate, display panel and display device Technical Field The disclosure relates to the technical field of display, in particular to an array substrate, a display panel and a display device. Background With the continuous development of display technology, display devices have been widely used. Common display devices may include Liquid crystal display devices (LCD) CRYSTAL DISPLAY and Organic Light-Emitting Diode (OLED) display devices. Among them, the liquid crystal display device has been attracting attention because of its small size, low power consumption, no radiation, high display resolution, and the like. Disclosure of utility model An embodiment of the disclosure is directed to an array substrate, a display panel and a display device, which are used for reducing the risk of short circuit between a data signal line and a first conductive layer. In order to achieve the above object, the embodiments of the present disclosure provide the following technical solutions: In one aspect, an array substrate is provided. The array substrate comprises a substrate and a first conductive layer, a first insulating layer, a semiconductor layer and a second conductive layer which are stacked along a direction away from the substrate. The semiconductor layer comprises a semiconductor pattern and a plurality of auxiliary patterns, wherein the semiconductor pattern is arranged at intervals with at least one auxiliary pattern, and the semiconductor pattern comprises an active layer of a transistor. The second conductive layer comprises a data signal line, the orthographic projection of the data signal line on the substrate and the orthographic projection of the side wall of the first conductive layer on the substrate are provided with N first areas which are overlapped with each other, the orthographic projection of the auxiliary patterns on the substrate covers M first areas, M is more than or equal to 2 and less than or equal to N, and M and N are positive integers. In the display panel, the thickness of the portion of the first insulating layer covering the sidewall of the first conductive layer is smaller, and the risk that the data signal line breaks down the first insulating layer at the sidewall of the first conductive layer is greater when the data signal line transmits the voltage signal. The semiconductor pattern and at least one auxiliary pattern are arranged at intervals, on one hand, the possibility that the auxiliary pattern is possibly irradiated by light is high, so that even if the auxiliary pattern generates some defect changes under the action of the light, the auxiliary pattern can not influence the stability of a switch (on-state voltage) of the transistor, and on the other hand, the auxiliary pattern and the semiconductor pattern are beneficial to reducing the total area of the auxiliary pattern and the semiconductor pattern, and further the consumable of the semiconductor layer is reduced. The first region is a portion where the side wall of the first conductive layer and the orthographic projection of the data signal line on the substrate overlap each other. The plurality of auxiliary patterns cover at least two first areas. Like this, auxiliary pattern can increase the interval between the lateral wall of data signal line and first conducting layer, and then increases the distance of electron motion between data signal line and the first conducting layer, even there is impurity particle in the first insulating layer, the auxiliary pattern of lateral wall that covers first insulating layer still is the insulating layer to can effectively reduce the risk of taking place the short circuit between data signal line and the first conducting layer, reduce array substrate's risk that takes place promptly. In some embodiments, the first conductive layer includes a plurality of gate lines extending in a first direction and spaced apart in a second direction, the first direction intersecting the second direction. The data signal line comprises a first main body part extending along the second direction and a source electrode part positioned at one side of the first main body part, wherein at least part of the orthographic projection of the source electrode part on the substrate is positioned in the orthographic projection range of the grid line on the substrate. In the first areas, the area where orthographic projections of the side walls of the first main body part and the grid lines on the substrate overlap with each other is a first subarea. The plurality of auxiliary patterns comprise first auxiliary patterns, the first auxiliary patterns and the semiconductor patterns are arranged along the first direction, and orthographic projection of the first auxiliary patterns on the substrate covers the first sub-region. In some embodiments, an orthographic projection of one of the first auxiliary patterns on the substrate covers one of the first sub-regions with a space between two adjacent first auxil