CN-224217091-U - Array memory device and memory equipment

CN224217091UCN 224217091 UCN224217091 UCN 224217091UCN-224217091-U

Abstract

The utility model discloses an array storage device and storage equipment, and relates to the technical field of data storage. The array storage device comprises a substrate, a data interface, a main control unit, a plurality of data storage units and each data storage unit, wherein the data interface is arranged on one side of the substrate, the main control unit is arranged on the substrate and is electrically connected with the data interface, the data storage units are arranged on the substrate and are respectively electrically connected with the main control unit, each data storage unit is used for storing at least one AI model, and the main control unit is used for receiving external data input by the data interface to the data storage units and/or outputting stored data of the data storage units to the data interface. The present utility model aims to improve the stability and rate of different AI model invocations provided in a plurality of data storage units.

Inventors

LIN YIN
LUO TING

Assignees

深圳市硅格半导体有限公司

Dates

Publication Date: 20260508
Application Date: 20250605

Claims (8)

1. An array memory device, the array memory device comprising: a substrate; The data interface is arranged on one side of the substrate; The main control unit is arranged on the substrate and is electrically connected with the data interface; The data storage units are arranged on the substrate and are respectively and electrically connected with the main control unit, and each data storage unit is used for storing at least one AI model; The main control unit is used for receiving external data input by the data interface to a plurality of data storage units and/or outputting stored data of the data storage units to the data interface.
2. The array storage device of claim 1, wherein the data interface comprises a gold finger.
3. The array storage device of claim 1, wherein the master unit comprises a RAID chip.
4. The array storage device of claim 1, wherein the data storage unit comprises: the data storage control circuit is electrically connected with the main control unit; the data storage circuits are respectively and electrically connected with the data storage control circuit; The data storage control circuit is used for receiving the control signal output by the main control unit and controlling the data storage circuit to output or store corresponding data.
5. The array storage device of claim 4, wherein the data storage control circuit comprises a CXL chip.
6. The array storage device of claim 4, wherein the data storage circuit comprises: The first storage circuits are respectively and electrically connected with the data storage control circuit and are used for storing data in a lasting mode; The second storage circuits are respectively and electrically connected with the data storage control circuit and are used for improving the storage and output speed of data.
7. The array memory device of claim 6, wherein the first memory circuit comprises a NAND chip and the second memory circuit comprises a DRAM chip.
8. A memory device comprising at least one array memory device as claimed in any one of claims 1 to 7.

Description

Array memory device and memory equipment Technical Field The present utility model relates to the field of data storage technologies, and in particular, to an array storage device and a storage device. Background Redundant arrays of independent disks (RAID, redundant array of INDEPENDENT DISKS), a key technology in the field of data storage, are dedicated to greatly improving the performance, reliability, and redundancy of data of a storage system. In the storage and use of the large data AI model, the connection between the disk and the array often depends on a plurality of interfaces in the traditional RAID architecture, so that the conditions of loose connection, poor contact and the like are easy to occur, hidden dangers are buried for stable data transmission, and instability exists in the invocation of the AI model. In addition, the connection between the disk and the array needs to be performed through an external data line, which results in that different AI models are stored in a plurality of hard disks, and when the AI models are switched, the problem of slow switching speed exists. Disclosure of utility model The utility model mainly aims to provide an array storage device and storage equipment, which aim to improve the stability and the speed of different AI model calls arranged in a plurality of data storage units. In order to achieve the above object, the present utility model provides an array memory device, comprising: a substrate; The data interface is arranged on one side of the substrate; The main control unit is arranged on the substrate and is electrically connected with the data interface; The data storage units are arranged on the substrate and are respectively and electrically connected with the main control unit, and each data storage unit is used for storing at least one storage AI model; The main control unit is used for receiving external data input by the data interface to a plurality of data storage units and/or outputting stored data of the data storage units to the data interface. In one embodiment, the data interface includes a golden finger. In an embodiment, the master unit comprises a RAID chip. In one embodiment, the data storage unit includes: the data storage control circuit is electrically connected with the main control unit; the data storage circuits are respectively and electrically connected with the data storage control circuit; The data storage control circuit is used for receiving the control signal output by the main control unit and controlling the data storage circuit to output or store corresponding data. In one embodiment, the data storage control circuit includes a CXL chip. In one embodiment, the data storage circuit comprises: The first storage circuits are respectively and electrically connected with the data storage control circuit and are used for storing data in a lasting mode; The second storage circuits are respectively and electrically connected with the data storage control circuit and are used for improving the storage and output speed of data. In one embodiment, the first memory circuit comprises a NAND chip and the second memory circuit comprises a DRAM chip. The utility model also proposes a memory device comprising at least one array memory means as claimed in any one of the preceding claims. According to the technical scheme, the array storage device is adopted, so that the stability and the speed of calling different AI models arranged in a plurality of data storage units are effectively improved. The array storage device comprises a substrate, a data interface, a main control unit and a plurality of data storage units. The data interface is arranged on one side of the substrate to output data stored in the array memory device and input external data. In addition, the main control unit is also arranged on the substrate and is electrically connected with the data interface, so that the data transmission processing is realized. The plurality of data storage units are also respectively arranged on the substrate and are respectively electrically connected with the main control unit through the substrate wiring so as to realize the storage and output of data. Wherein each data storage unit is used for storing at least one AI model. The data storage units are electrically connected with the main control unit on the same substrate, so that the stability and the speed of calling different AI models in the data storage units are effectively improved. Drawings In order to more clearly illustrate the embodiments of the present utility model or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, and it is obvious that the drawings in the following description are only some embodiments of the present utility model, and other drawings may be obtained according to the structures shown in these drawings without inventive effort for a person skilled in t