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CN-224217094-U - Signal output circuit, chip and vehicle

CN224217094UCN 224217094 UCN224217094 UCN 224217094UCN-224217094-U

Abstract

The application is suitable for the technical field of chip design, and provides a signal output circuit, a chip and a vehicle. The signal output circuit comprises a first selection unit arranged in the chip and an instruction input unit arranged in the chip, wherein the instruction input unit is connected with the control end of the first selection unit, a plurality of input ends of the first selection unit are used for being correspondingly connected with the output ends of a plurality of monitoring units in the chip, the output end of the first selection unit is used for being connected with one pin of the chip, the instruction input unit is used for receiving a first selection instruction and transmitting the first selection instruction to the first selection unit, and the first selection unit is used for outputting signals output by a first target monitoring unit in the plurality of monitoring units to the pin of the chip according to the first selection instruction. The plurality of input ends of the first selection unit are respectively connected with the plurality of monitoring units, the output end of the first selection unit is connected with one pin of the chip, and only one chip pin is needed, so that the size of the chip is reduced.

Inventors

  • WANG JUNWEI
  • CAO CHANGFENG

Assignees

  • 湖南紫荆半导体有限公司

Dates

Publication Date
20260508
Application Date
20250430

Claims (10)

  1. 1. The signal output circuit is characterized by comprising a first selection unit arranged in a chip and an instruction input unit arranged in the chip, wherein the instruction input unit is connected with a control end of the first selection unit, a plurality of input ends of the first selection unit are used for being correspondingly connected with output ends of a plurality of monitoring units in the chip, and the output end of the first selection unit is used for being connected with one pin of the chip; The first selecting unit is used for outputting signals output by a first target monitoring unit in the plurality of monitoring units to pins of the chip according to the first selecting instruction.
  2. 2. The signal output circuit of claim 1, wherein the first selection unit comprises a first selection switch, a control terminal of the first selection switch is connected to the command input unit, a plurality of input terminals of the first selection switch are used for being correspondingly connected to output terminals of a plurality of monitoring units in the chip, and an output terminal of the first selection switch is used for being connected to one pin of the chip.
  3. 3. The signal output circuit according to claim 2, further comprising a second selection unit, a control terminal of the second selection unit being connected to the instruction input unit, a plurality of input terminals of the second selection unit being adapted to be correspondingly connected to output terminals of a plurality of monitoring units in the chip, an output terminal of the second selection unit being connected to one input terminal of the first selection switch; The instruction input unit is also used for receiving a second selection instruction and transmitting the second selection instruction to the second selection unit, and the second selection unit is used for outputting signals output by a second target monitoring unit in the plurality of monitoring units to the first selection switch according to the second selection instruction.
  4. 4. A signal output circuit according to claim 3 wherein the second selection unit comprises at least one second selection switch, the control terminal of each second selection switch being connected to the command input unit, the plurality of inputs of each second selection switch being adapted to be correspondingly connected to the outputs of the plurality of monitoring units within the chip, the output of each second selection switch being connected to one input of the first selection switch.
  5. 5. The signal output circuit according to claim 4, further comprising a third selection unit, wherein a control terminal of the third selection unit is connected to the instruction input unit, a plurality of input terminals of the third selection unit are used for being correspondingly connected to output terminals of a plurality of monitoring units in the chip, and an output terminal of the third selection unit is connected to an input terminal corresponding to the second selection switch; The instruction input unit is further configured to receive a third selection instruction and transmit the third selection instruction to the third selection unit, where the third selection unit is configured to output a signal output by a third target monitoring unit of the plurality of monitoring units to the second selection switch according to the third selection instruction.
  6. 6. The signal output circuit of claim 5 wherein the third selection unit comprises at least one third selection switch, the control terminal of each third selection switch being connected to the command input unit, the plurality of input terminals of each third selection switch being adapted to be connected to the output terminals of the plurality of monitoring units in the chip, the output terminal of each third selection switch being connected to one input terminal of the corresponding second selection switch.
  7. 7. The signal output circuit of claim 6 wherein the first selector switch is coupled to a monitor cell in a first region of the chip, the second selector switch is coupled to a monitor cell in a second region of the chip, and the third selector switch is coupled to a monitor cell in a third region of the chip, the first region, the second region, and the third region being non-coincident with one another.
  8. 8. The signal output circuit of claim 6 wherein the instruction input unit comprises a register connected to the on-chip bus, the register being connected to the control terminals of the first selector switch, the control terminals of all the second selector switches, and the control terminals of all the third selector switches, respectively.
  9. 9. A chip comprising the signal output circuit of any one of claims 1 to 8.
  10. 10. A vehicle comprising the chip of claim 9.

Description

Signal output circuit, chip and vehicle Technical Field The application belongs to the technical field of chip design, and particularly relates to a signal output circuit, a chip and a vehicle. Background Chips can fail in some situations, for example, chips are prone to failure at extreme temperatures, and chips are prone to failure when they receive strong electromagnetic interference. At present, a plurality of monitoring units are arranged in some chips and used for monitoring a plurality of different functional modules, and when some functional modules fail, the corresponding monitoring units can output alarm signals. In order for the monitoring units to output alarm signals off-chip, each monitoring unit needs to be connected with one pin of the chip, thereby increasing the pins of the chip. Disclosure of utility model The embodiment of the application provides a signal output circuit, a chip and a vehicle, which can solve the problem that a plurality of monitoring units need to use a plurality of pins of the chip, so that the pins of the chip are increased. In a first aspect, an embodiment of the present application provides a signal output circuit, including a first selection unit disposed in a chip and an instruction input unit disposed in the chip, where the instruction input unit is connected to a control end of the first selection unit, multiple input ends of the first selection unit are used for being correspondingly connected to output ends of multiple monitoring units in the chip, and an output end of the first selection unit is used for being connected to one pin of the chip; The first selecting unit is used for outputting signals output by a first target monitoring unit in the plurality of monitoring units to pins of the chip according to the first selecting instruction. In a possible implementation manner of the first aspect, the first selection unit includes a first selection switch, a control end of the first selection switch is connected to the instruction input unit, multiple input ends of the first selection switch are used for being correspondingly connected to output ends of multiple monitoring units in the chip, and an output end of the first selection switch is used for being connected to one pin of the chip. In a possible implementation manner of the first aspect, the signal output circuit further includes a second selection unit, a control end of the second selection unit is connected to the instruction input unit, multiple input ends of the second selection unit are used for being correspondingly connected to output ends of multiple monitoring units in the chip, and an output end of the second selection unit is connected to one input end of the first selection switch; The instruction input unit is also used for receiving a second selection instruction and transmitting the second selection instruction to the second selection unit, and the second selection unit is used for outputting signals output by a second target monitoring unit in the plurality of monitoring units to the first selection switch according to the second selection instruction. In a possible implementation manner of the first aspect, the second selection unit includes at least one second selection switch, a control end of each second selection switch is connected to the instruction input unit, multiple input ends of each second selection switch are used for being correspondingly connected to output ends of multiple monitoring units in the chip, and an output end of each second selection switch is connected to one input end of the first selection switch. In a possible implementation manner of the first aspect, the signal output circuit further includes a third selection unit, a control end of the third selection unit is connected to the instruction input unit, multiple input ends of the third selection unit are used for being correspondingly connected to output ends of multiple monitoring units in the chip, and an output end of the third selection unit is connected to an input end corresponding to the second selection switch; The instruction input unit is further configured to receive a third selection instruction and transmit the third selection instruction to the third selection unit, where the third selection unit is configured to output a signal output by a third target monitoring unit of the plurality of monitoring units to the second selection switch according to the third selection instruction. In a possible implementation manner of the first aspect, the third selection unit includes at least one third selection switch, a control end of each third selection switch is connected to the instruction input unit, multiple input ends of each third selection switch are used for being correspondingly connected to output ends of multiple monitoring units in the chip, and an output end of each third selection switch is connected to one input end corresponding to the second selection switch. In a possible implementatio