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CN-224217095-U - Heterogeneous data acquisition recording device

CN224217095UCN 224217095 UCN224217095 UCN 224217095UCN-224217095-U

Abstract

The application discloses a heterogeneous data acquisition and recording device, which relates to the technical field of data acquisition and storage and comprises an input interface, a main control circuit, a storage circuit, a downloading interface and a power supply circuit, wherein the input interface is used for accessing DI signals, AD signals and SPI signals, the main control circuit comprises a main control chip, the main control circuit is connected with the input interface, the single chip is connected with the main control circuit, the storage circuit is connected with the single chip and is used for storing DI data, AD data and SPI data output by the single chip, the downloading interface is connected with the single chip and is used for connecting an upper computer, and the power supply circuit is connected with the input interface and the downloading interface and is used for supplying power to the main control circuit and the single chip. The application adopts a heterogeneous mode of combining the main control chip and the singlechip, effectively combines the high expansion performance of the ZYNQ processor with the low cost of the STM series singlechip, and reduces the cost on the premise of ensuring that the performance meets the requirement.

Inventors

  • WANG KANG
  • Yuan Haogang
  • Jin Hanghang

Assignees

  • 西安凌凯电子科技有限公司

Dates

Publication Date
20260508
Application Date
20250618

Claims (9)

  1. 1. A heterogeneous data acquisition recording device, comprising: the input interface is used for accessing DI signals, AD signals and SPI signals; The main control circuit comprises a main control chip with the model of XC7Z020-2CLG484I, and is connected with the input interface; The singlechip is a chip with the model of STM32F427IIH6 and is connected with the main control circuit; The storage circuit is connected with the singlechip and is used for storing DI data, AD data and SPI data output by the singlechip; the downloading interface is connected with the singlechip and is used for connecting with an upper computer; And the power supply circuit is connected with the input interface and the downloading interface and is used for supplying power to the main control circuit, the singlechip and the storage circuit.
  2. 2. A heterogeneous data acquisition and recording device according to claim 1 wherein said input interface employs a 24-core connector, said 24-core connector being capable of simultaneously accessing 2 of said DI signals, 7 of said AD signals and 2 of said SPI signals.
  3. 3. The heterogeneous data acquisition and recording device according to claim 1, wherein an input end of the main control chip is connected with a DI conditioning circuit, an AD acquisition circuit and an SPI filter circuit, and the DI conditioning circuit, the AD acquisition circuit and the SPI filter circuit are respectively used for accessing the DI signal, the AD signal and the SPI signal.
  4. 4. The heterogeneous data acquisition and recording device according to claim 3, wherein a signal conditioning circuit is connected between the input interface and the DI conditioning circuit, and the signal conditioning circuit is used for isolating an 8-15V input power supply input by the input interface from the DI conditioning circuit through an optocoupler.
  5. 5. The heterogeneous data collection recording device according to claim 1, wherein the memory circuit is an eMMC memory chip with a model number SDINBDG 4-8G-XA.
  6. 6. The heterogeneous data acquisition and recording device according to claim 1, wherein a switching circuit is connected between the download interface and the single chip microcomputer.
  7. 7. The heterogeneous data collection and recording device according to claim 6, wherein the switching circuit adopts an expansion chip with a model number of USB3300-EZK, and the switching circuit is used for realizing a high-speed USB function of the singlechip.
  8. 8. The heterogeneous data collection recording device according to claim 1, wherein the power supply circuit comprises a power supply switching circuit, an input end of the power supply switching circuit is connected with the input interface and the downloading interface respectively, the power supply switching circuit comprises a first power supply switching chip with a model number of MT2492 and a power supply switching chip with a model number of TPS211 2115APWR, the first power supply switching chip is connected between the input interface and the first input end of the power supply switching chip, a second input end of the power supply switching chip is connected with the downloading interface, the first power supply switching chip is used for converting 8-15V input power supplied by the input interface into 5V power, and the power supply switching chip is used for switching between 5V power supplied by the first power supply switching chip and 5V power supplied by the downloading interface.
  9. 9. The heterogeneous data acquisition and recording device according to claim 8, wherein the power supply circuit further comprises a power supply conversion circuit, the power supply conversion circuit comprises three second power supply conversion chips with model number TPS82085SIL, the input ends of the second power supply conversion chips are connected with the output ends of the power supply switching chips, and the three second power supply conversion chips respectively output 3.3V, 1.8V and 1.2V power supplies to the main control chip, the single chip microcomputer and the storage circuit.

Description

Heterogeneous data acquisition recording device Technical Field The application relates to the technical field of data acquisition and storage, in particular to a heterogeneous data acquisition and recording device. Background During operation of various mechanical devices, such as civilian or military devices, various data are generated that reflect the operating state of the device, and thus the collection and storage of such data facilitates the monitoring and analysis of the device state. Because the equipment to be monitored is more in variety, the data types are in various states, and the expansibility of the data acquisition and recording device is required to be stronger so as to be compatible with different data types in order to meet the acquisition and storage requirements of various different data. Aiming at the requirement, the method is designed by adopting a ZYNQ architecture-based process, and the processor integrates an FPGA and an ARM processor and has stronger expansion capability. However, the expansion capability of a single ZYNQ processor is limited, and when input data occupies most interfaces, the remaining interfaces are often insufficient to support storage and reading, so that when the expansion requirement is relatively high, multiple ZYNQ processors are inevitably required to be used. However, the cost of the ZYNQ processor is relatively high, and the use of multiple ZYNQ processors results in a relatively high overall cost of the data acquisition recording device. Disclosure of utility model The embodiment of the application provides a heterogeneous data acquisition and recording device which is used for solving the problem of higher cost caused by using a plurality of ZYNQ processors in the prior art. The embodiment of the application provides a heterogeneous data acquisition and recording device, which comprises: the input interface is used for accessing DI signals, AD signals and SPI signals; the main control circuit comprises a main control chip with the model of XC7Z020-2CLG484I, and is connected with the input interface; the singlechip adopts a chip with the model of STM32F427IIH6 and is connected with the main control circuit; The storage circuit is connected with the singlechip and used for storing DI data, AD data and SPI data output by the singlechip; the downloading interface is connected with the singlechip and is used for connecting with the upper computer; and the power supply circuit is connected with the input interface and the downloading interface and is used for supplying power to the main control circuit, the singlechip and the storage circuit. In one possible implementation, the input interface employs a 24-core connector, which enables simultaneous access to 2 DI signals, 7 AD signals, and 2 SPI signals. In one possible implementation manner, an input end of the main control chip is connected with a DI conditioning circuit, an AD acquisition circuit and an SPI filter circuit, and the DI conditioning circuit, the AD acquisition circuit and the SPI filter circuit are respectively used for accessing DI signals, AD signals and SPI signals. In one possible implementation, a signal conditioning circuit is connected between the input interface and the DI conditioning circuit, and the signal conditioning circuit is used for isolating an 8-15V input power supply input by the input interface from the DI conditioning circuit through an optocoupler. In one possible implementation, the memory circuit employs an eMMC memory chip model SDINBDG 4-8G-XA. In one possible implementation, a switching circuit is connected between the download interface and the single chip microcomputer. In one possible implementation, the switching circuit employs an expansion chip of type USB3300-EZK, which is used to implement the high-speed USB function of the single chip. In one possible implementation manner, the power supply circuit includes a power supply switching circuit, an input end of the power supply switching circuit is connected with the input interface and the downloading interface respectively, the power supply switching circuit includes a first power supply conversion chip with a model number of MT2492 and a power supply switching chip with a model number of TPS2115APWR, the first power supply conversion chip is connected between the input interface and the first input end of the power supply switching chip, a second input end of the power supply switching chip is connected with the downloading interface, the first power supply conversion chip is used for converting 8-15V input power supplied by the input interface into 5V power, and the power supply switching chip is used for switching between the 5V power supplied by the first power supply conversion chip and the 5V power supplied by the downloading interface. In one possible implementation manner, the power supply circuit further comprises a power supply conversion circuit, the power supply conversion circuit comprises thr