CN-224217106-U - Desktop card sender

Abstract

The utility model relates to the technical field of card issuers, and in order to solve the technical problems of unstable radio frequency signal emission, low communication rate and poor system adaptability of the existing card issuers, the utility model discloses a desktop card issuer, a radio frequency receiving and transmitting circuit comprises a double-emission channel and a single-receiving channel, which are respectively connected with an antenna port through a matching circuit, wherein the matching circuit comprises an inductor L3 and an inductor L4, a TX1 end of the double-emission channel is sequentially connected with the antenna port ANT1 through the inductor L3 and the capacitor C34, the TX1 end of the emission channel is sequentially grounded through the inductor L3, the capacitor C34 and the capacitor C14, a TX2 end of the emission channel is sequentially connected with a 2 nd end of the inductor L3 through the inductor L4, the capacitor C35, the capacitor C15 and the capacitor C14, the TX2 end of the emission channel is sequentially grounded through the inductor L4 and the capacitor C13, effective synthesis and impedance matching of a double-path signal are realized, harmonic wave and spurious signals are restrained, and radio frequency signal quality is improved.

Inventors

• QI CUIXIA
• SHEN HAIMING

Assignees

• 深圳市新润晖智能卡有限公司

Dates

Publication Date

20260508

Application Date

20250612

Claims (4)

1. 1. The desktop card sender comprises a microcontroller (U2), an RFID module (U1) and a radio frequency receiving and transmitting circuit, wherein the radio frequency receiving and transmitting circuit comprises a double-transmitting channel and a single-receiving channel, the double-transmitting channel is connected with an antenna port ANT1 and an antenna port ANT2 through a matching circuit respectively, the matching circuit comprises an inductor L3 and an inductor L4, the TX1 end of the double-transmitting channel is sequentially connected with the antenna port ANT1 through the inductor L3 and the capacitor C34, the TX1 end of the transmitting channel is sequentially grounded through the inductor L3, the capacitor C34 and the capacitor C14, the TX2 end of the transmitting channel is sequentially connected with the 2 nd end of the inductor L3 through the inductor L4, the capacitor C13 and the capacitor C11, the TX2 end of the transmitting channel is sequentially connected with the antenna port ANT1 through the inductor L4, the capacitor C35 and the capacitor C15, and the TX2 end of the transmitting channel is sequentially grounded through the inductor L4 and the capacitor C13, and the inductor L3, the inductor C4, the capacitor C34, the capacitor C11 and the capacitor C14 form a pi filter circuit.
2. 2. The desktop card issuer according to claim 1, wherein an RX end of the receiving channel is connected to the antenna port ANT2 through a resistor R18 and a capacitor C36 in sequence, and a TX2 end of the transmitting channel is connected to the antenna port ANT2 through an inductor L4 and a capacitor C35 in sequence.
3. 3. The desktop card issuer of claim 2, wherein XTAL1 and XTAL2 ports of the RFID module (U1) are connected to a crystal oscillator (Y1), with both sides grounded to a capacitor to provide a clock signal.
4. 4. A desktop card sender according to claim 3, characterized in that the microcontroller (U2) is connected to the RFID module (U1) via an SPI bus.

Description

Desktop card sender Technical Field The utility model relates to the technical field of card issuers, in particular to a desktop card issuer. Background With the rapid development of the internet of things technology, radio frequency identification (RFID, radio Frequency Identification) technology is widely applied to various fields such as logistics management, access control, asset tracking and the like. In practical application, the performance of an RFID reader (also called a card reader) is used as a core device, which directly affects the recognition efficiency and stability of the system. Most of the existing RFID card issuers adopt a single-ended transmitting design, and radio frequency signals are easily affected by harmonic interference and poor matching of antenna ports on a transmitting path, so that the identification distance is shortened, the identification precision is reduced, and even the system stability is reduced. In addition, part of equipment ignores noise filtering of a receiving path in signal processing and is matched with a front end, so that the response capability of a system to a tag is not strong, and the anti-interference capability is not enough. In the aspect of radio frequency circuit design, how to realize efficient synthesis, harmonic suppression and antenna matching of two-way radio frequency signals is always a key for improving the performance of the card sender. Meanwhile, the data communication mode between the main control and the RFID module also affects the communication efficiency and the system response speed of the whole machine, and the traditional I2C interface and other interfaces often have rate bottlenecks in a high-frequency scene, so that the high-performance application requirements are difficult to meet. Therefore, a desktop RFID card issuer with compact structure, high signal integrity and stable communication is needed to optimize the design of the radio frequency receiving and transmitting path, improve the communication efficiency and the overall performance of the system, and meet the actual requirements of new generation RFID applications. Disclosure of utility model The utility model aims to provide a desktop card sender to solve the technical problems of unstable radio frequency signal emission, low communication rate and poor system adaptability of the existing card sender. In order to achieve the above purpose, the utility model provides a desktop card sender, which comprises a microcontroller, an RFID module and a radio frequency receiving and transmitting circuit, wherein the radio frequency receiving and transmitting circuit comprises a double-transmitting channel and a single-receiving channel which are respectively connected with a matching circuit, an antenna port ANT1 and an antenna port ANT2, the matching circuit comprises an inductor L3 and an inductor L4, the TX1 end of the double-transmitting channel is sequentially connected with the antenna port ANT1 through the inductor L3 and a capacitor C34, the TX1 end of the transmitting channel is sequentially grounded through the inductor L3, the capacitor C34 and the capacitor C14, the TX2 end of the transmitting channel is sequentially connected with the 2 nd end of the inductor L3 through the inductor L4, the capacitor C13 and the capacitor C11, the TX2 end of the transmitting channel is sequentially connected with the antenna port ANT1 through the inductor L4, the capacitor C35 and the capacitor C15, and the TX2 end of the transmitting channel is sequentially grounded through the inductor L4, the capacitor C13, the inductor L4, the capacitor C34, the capacitor C11, the capacitor C13 and the capacitor C14 are sequentially formed into a pi-shaped filter circuit. According to the utility model, the double-emission channel is connected with the antenna port ANT1 through the pi-shaped filter circuit formed by the inductors L3 and L4 and the capacitors, so that the effective synthesis and impedance matching of two-way signals are realized, harmonic and stray signals can be obviously restrained, the transmission efficiency and emission quality of radio frequency signals are improved, meanwhile, the receiving channel is connected to the ANT2 through front end matching, the receiving sensitivity is enhanced, the overall structure improves the radio frequency performance and the system stability, and the beneficial effects of longer identification distance, higher identification precision and more reliable communication are realized. Further, the RX end of the receiving channel is connected with the antenna port ANT2 through a resistor R18 and a capacitor C36 in sequence, and the TX2 end of the transmitting channel is connected with the antenna port ANT2 through an inductor L4 and a capacitor C35 in sequence. The RX end of the receiving channel is connected with the antenna port ANT2 through the resistor R18 and the capacitor C36 in sequence, the TX2 end of the transmitting channel is connected