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CN-224218283-U - Circuit structure for reducing chip heating through voltage dividing resistor

CN224218283UCN 224218283 UCN224218283 UCN 224218283UCN-224218283-U

Abstract

The utility model provides a circuit structure for reducing chip heating through a voltage dividing resistor, which comprises a power management circuit, a second path of power input port, a VDDI and a plurality of low dropout linear voltage regulators LDOs, wherein the first path of power input port is used for receiving external input voltage, the input voltage is 3.3V direct current, the second path of power input port is independent of the first path of power input port and is used for supplying power to the outside of a core logic circuit, the VDDI is connected with a power switch LDO_EN for controlling the on-off of the second path of power, and is the name of a power supply input pin of a chip core or refers to the power supply input of the chip core, a resistor is connected to the input circuit of the VDDI and is used for dividing the voltage, namely the voltage dividing resistor, so that the input voltage of the VDDI is reduced, and the plurality of low dropout linear voltage regulators LDOs are used for converting the input voltage into different output voltages. After the built-in LDO realizes voltage conversion, the circuit structure of the chip heating is reduced through the voltage dividing resistor, and the problem of serious chip heating is solved.

Inventors

  • JIANG ZHONGQIN

Assignees

  • 合肥君正科技有限公司

Dates

Publication Date
20260508
Application Date
20250508

Claims (8)

  1. 1. The circuit structure for reducing the heating of the chip through the voltage dividing resistor is characterized by comprising a power management circuit, and comprises: the first path of power input port is used for receiving external input voltage, and the input voltage is 3.3V direct current; the second path of power input port is independent of the first path of power input port and is used for supplying power to the outside of the core logic circuit; VDDIN connected with a power switch LDO_EN for controlling the on-off of the second path of power supply, wherein the VDDIN is the name of a power supply input pin of the chip core or refers to the power supply input of the chip core; A resistor is connected to the input circuit of VDDIN for dividing voltage, namely a voltage dividing resistor, so as to reduce the input voltage of VDDIN; The LDOs are used for converting input voltages into different output voltages.
  2. 2. The circuit structure for reducing heat generation of a chip by voltage dividing resistance according to claim 1, further comprising: A first LDO3 for converting the input voltage into a first output voltage and supplying the first output voltage to the core logic circuit; A second LDO2 converts the input voltage into a second output voltage and supplies the second output voltage to the AON module; The third LDO1 converts the input voltage into a third output voltage, and supplies the third output voltage to the physical layer interface circuit.
  3. 3. The circuit structure for reducing heat generation of a chip through a voltage dividing resistor according to claim 2, wherein the input voltage is 3.3V dc, the first output voltage is 0.9V, the second output voltage is 0.9V, the third output voltage is 1.8V, the Core logic circuit is C200 Core Logics, the AON module is C200 AON, and the physical layer interface circuit is C200.8V IO/MIPI PHY.
  4. 4. The circuit configuration for reducing heat generation of a chip by voltage dividing resistance according to claim 1, wherein the circuit further comprises: a direct power distribution path for directly supplying the input voltage to another physical layer interface circuit; A power distribution path supplies a third output voltage to the low voltage input-output interface.
  5. 5. The circuit structure of claim 4, wherein the other physical layer interface circuit is C200.3V IO/USB PHY/RC and the low voltage input/output interface is VDDIO33.
  6. 6. The circuit structure for reducing heat generation of a chip by voltage dividing resistance according to claim 1, further comprising: And the enabling control circuit is used for controlling the enabling ends of the low dropout linear regulators to realize dynamic control of the output voltage, and the circuit is LDO_EN.
  7. 7. The circuit configuration according to any one of claims 1 to 6, wherein the resistance of the resistor is determined according to a required voltage dividing ratio to ensure that the input voltage of VDDIN meets the operating voltage requirement of the core logic circuit.
  8. 8. The circuit structure for reducing heat generation of a chip by a voltage dividing resistor according to claim 7, further comprising: two-way power input: The first power supply input, VDDIO33 is 3.3V input of the chip, the power supply sources of the LDO are VDDIO33, and the LDO works by converting the voltage input by VDDIN and VDDIO33 to output the required voltage; A second power input, independent of the first power input, for providing external power to the C200 Core Logics, said VDDIN being the power input to the C200 Core Logics; Voltage dividing resistor: the divider resistor is connected to an external input circuit of the C200 Core Logics and is used for reducing the input voltage of VDDIN so as to reduce the heating of the chip; LDO voltage regulator: LD03 connected to VDDIN for regulating the input voltage xV to 0.9V and providing power for the C200 Core Logics; LD02 connected to VDDIO33 for regulating 3.3V input voltage to 0.9V and providing power for C200 AON; LD01, connected to VDDIO33, for regulating 3.3V input voltage to 1.8V and providing power for VDDI018 and C200 1.8V IO/MIPI PHY; enabling signal control: The LDO3_EN signal is connected to the LD03 and used for controlling the enabling or disabling of the LD 03; The LDO1_EN signal is connected to the LD01 and used for controlling the enabling or disabling of the LD 01; core logic circuitry: C200 Core Logics connected to the output of LD03, powered by the 0.9V voltage provided by LD03, for performing the main calculation and control functions of the system; AON module power: C200 An AON connected to the output end of LD02, powered by 0.9V voltage provided by LD02, for system monitoring and wake-up functions in low power mode; I/O and USB power: VDDI033, connected to the 3.3V power input, for providing 3.3V power to the C200.3V IO/USB PHY/RC; c200 3.3V IO/USB PHY/RC connected to VDDI033 for communication functions of I/O and USB interfaces; 1.8V I/O and MIPI PHY: VDDI018, connected to the output of LD01, powered by LD01 supplied 1.8V voltage, for powering C200.8V IO/MIPI PHY and CIS; c200 1.8V IO/MIPI PHY connected to VDDI018 for communication functions of 1.8V I/O and MIPI interfaces; An image sensor: CIS, connected to VDDI018, powered by the 1.8V voltage provided by LD01, for capturing image data.

Description

Circuit structure for reducing chip heating through voltage dividing resistor Technical Field The utility model belongs to the field of design of semiconductor integrated circuits, and particularly relates to a circuit structure for reducing chip heating through a voltage dividing resistor. Background In the prior art, in the field of chip design, control heating has a vital meaning. The performance and stability of a chip as a core component of modern electronic devices are directly related to the operation of the whole system. The chip inevitably generates heat during operation, and if not controlled effectively, a series of serious problems will be caused. The heating is effectively controlled in the chip design, so that the performance and the reliability of the chip are not only concerned, but also key factors for ensuring the successful performance of the chip verification and improving the verification accuracy and efficiency are ensured. The power supply design of the prior pen-powered ISP chip is mainly realized based on a low dropout linear regulator LDO, and the input 3.3V/5V voltage is converted into the voltage required by the chip to work through the LDO. The design of the LDO inside the chip is mainly because the area of the PCB of the ISP module is very small (the height is not more than 2mm generally), and it is difficult to place the LDO on the PCB with such small size, if the number of LDOs is large, it is difficult to place and route. That is, in the prior art, a designer of a pen-powered ISP chip generally adopts a scheme of incorporating LDO into the chip. However, the LDO is built in the chip, and the prior art scheme has the following defects that the LDO is seriously heated, so that the chip is seriously heated. Furthermore, technical terms in the art include: core, the digital logic portion of the chip, most digital modules including the chip CPU. Disclosure of utility model In order to solve the problems, the application aims to solve the problem of serious chip heating by reducing the chip heating circuit structure through the divider resistor after the built-in LDO realizes voltage conversion. Specifically, the present utility model provides a circuit configuration for reducing heat generation of a chip by a voltage dividing resistor, the circuit configuration including a power management circuit, comprising: the first path of power input port is used for receiving external input voltage, and the input voltage is 3.3V direct current; the second path of power input port is independent of the first path of power input port and is used for supplying power to the outside of the core logic circuit; The power supply control circuit comprises a power switch LDO_EN, a resistor and a power switch, wherein the power switch LDO_EN is connected with the power switch LDO_EN for controlling the on-off of a second path of power, and the VDDI is the name of a power supply input pin of a chip core or refers to the power supply input of the chip core; The LDOs are used for converting input voltages into different output voltages. The circuit structure further includes: A first LDO3 for converting the input voltage into a first output voltage and supplying the first output voltage to the core logic circuit; A second LDO2 converts the input voltage into a second output voltage and supplies the second output voltage to the AON module; The third LDO1 converts the input voltage into a third output voltage, and supplies the third output voltage to the physical layer interface circuit. The input voltage is 3.3V direct current, the first output voltage is 0.9V, the second output voltage is 0.9V, the third output voltage is 1.8V, the Core logic circuit is C200Core Logics, the AON module is C200 AON, and the physical layer interface circuit is C2001.8V IO/MIPIPHY. The circuit further comprises: A direct power distribution path for directly supplying the input voltage to another physical layer interface circuit, and a power distribution path for supplying the third output voltage to the low voltage input/output interface. The other physical layer interface circuit is C200.3V IO/USB PHY/RC, and the low voltage input/output interface is VDDIO33. The circuit structure further includes: And the enabling control circuit is used for controlling the enabling ends of the low dropout linear regulators to realize dynamic control of the output voltage, and the switching circuit is LDO_EN. The resistance of the resistor is determined according to the required voltage division ratio so as to ensure that the input voltage of the VDDIN meets the working voltage requirement of the core logic circuit. The circuit structure further includes: two-way power input: The first power supply input, VDDIO33 is 3.3V input of the chip, the power supply sources of the LDO are VDDIO33, and the LDO works by converting the voltage input by VDDIN and VDDIO33 to output the required voltage; A second power input, independent of the first pow