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CN-224218287-U - Power control chip with variable sampling blanking time

CN224218287UCN 224218287 UCN224218287 UCN 224218287UCN-224218287-U

Abstract

The utility model relates to a power electronics technical field discloses a variable sampling blanking time's power control chip, including high voltage power supply unit, reference unit, comparator CMP1 to comparator CMP4, switch SW1 to switch SW6, controlled current source G1, controlled current source G2, electric capacity C1 to electric capacity C4, pulse generation unit, rising edge delay unit, D trigger DFF1, SR latch SR1, BUFFER BUFFER AND AND gate AND1; the utility model discloses when using, when outside MOS pipe on-time is longer, the higher voltage on electric capacity C1, when outside MOS pipe turns off, controlled current source G2's output current is less to lead to electric capacity C2's charge time longer, and then make comparator CMP 2's output upset's time extension, the effect of finally producing is the blanking time of voltage VAUX sampling is longer when the primary side electric current of transformer is higher, has realized sampling blanking time variable, can guarantee to input the sampling voltage of switch SW3 and can truly reflect output voltage, avoid the system output error to appear.

Inventors

  • GU JIE

Assignees

  • 江苏源微半导体科技有限公司

Dates

Publication Date
20260508
Application Date
20250512

Claims (10)

  1. 1. The power supply control chip with the variable sampling blanking time is characterized by comprising a comparator CMP1, a D trigger DFF1, an SR latch SR1 and a BUFFER BUFFER; The positive input end of the comparator CMP1 is used for inputting a reference voltage VZCD, the negative input end of the comparator CMP1 is respectively and electrically connected with the output end of the switch SW3 and the input end of the switch SW4, the input end of the switch SW3 is used for accessing output feedback voltage, the control end of the switch SW3 is respectively and electrically connected with the output end of the comparator CMP2 and the input end of the pulse generating unit, the output end of the pulse generating unit is electrically connected with the control end of the switch SW4, the positive input end of the comparator CMP2 is respectively and electrically connected with one end of the capacitor C2, the input end of the switch SW5 and the output end of the controlled current source G2, the negative input end of the comparator CMP2 is used for inputting a reference voltage VDELAY V, the output end of the controlled current source G2 is used for accessing the reference voltage V5V, and the positive connection end of the controlled current source G2 is used for accessing the reference voltage VREF2; The output end of the switch SW4 IS electrically connected with the negative connection end of the controlled current source G1 AND IS grounded through a capacitor C3, the positive connection end of the controlled current source G1 IS used for inputting a reference voltage VREF, the input end of the controlled current source G1 IS used for accessing a reference voltage V5V, the output end of the controlled current source G1 IS electrically connected with the negative input end of the comparator CMP4 AND IS used for inputting a current IS1, the positive input end of the comparator CMP4 IS respectively electrically connected with one end of the capacitor C4 AND the input end of the switch SW6, the other end of the capacitor C4 AND the output end of the switch SW6 are grounded, the output end of the comparator CMP4 AND one input end of the AND gate AND1 are electrically connected, the output end of the AND gate AND1 IS electrically connected with the R input end of the SR latch SR1, the other input end of the AND gate AND1 IS electrically connected with the input end of the comparator CMP3, the negative input end of the comparator CMP3 IS used for inputting a reference voltage VCS_MIN, the positive input end of the comparator CMP3 IS respectively electrically connected with the output end of the switch SW2 AND the output end of the switch SW1, the input end of the switch SW2 IS electrically connected with the rising edge of the control unit through the capacitor C1 AND the input end of the switch SW 1; the output end of the comparator CMP1 is electrically connected with the clock input end of the D trigger DFF1, the Q output end of the D trigger DFF1 is electrically connected with the S input end of the SR latch SR1, the QP output end of the SR latch SR1 is respectively electrically connected with the input end of the BUFFER BUFFER, the reset end of the D trigger DFF1 and the control end of the switch SW5, and the QN output end of the SR latch SR1 is electrically connected with the control end of the switch SW 6.
  2. 2. The power control chip of claim 1, further comprising a high voltage power supply unit that generates a VCC voltage based on an external input voltage, and a reference unit that generates a reference voltage V5V, a reference voltage VZCD, a reference voltage VREF2, a reference voltage vcs_min, and a reference voltage VDELAY based on the VCC voltage.
  3. 3. The power control chip with variable sampling blanking time according to claim 2, further comprising a chip body 100, wherein the high voltage power supply unit, the reference unit, the comparators CMP1 to CMP4, the switches SW1 to SW6, the controlled current source G1, the controlled current source G2, the capacitors C1 to C4, the pulse generating unit, the rising edge delay unit, the D flip-flop DFF1, the SR latch SR1, the BUFFER, AND the AND gate AND1 are all disposed on the chip body.
  4. 4. The power control chip with variable sampling blanking time according to claim 3, wherein the chip body is further provided with an HV pin, a VCC pin, an FB pin, a COMP pin, a GND pin, a GATE pin, and a CS pin; The high-voltage power supply circuit comprises a high-voltage power supply unit, a high-voltage power supply (HV) pin, a high-voltage power supply unit, a high-voltage power supply (VCC) pin, a high-voltage power Supply (SW) pin, a high-voltage power supply (FB) pin, a Switch (SW) pin, a controlled current source (G1) and a controlled current source (COMP) pin, wherein the HV pin is electrically connected with the input end of the high-voltage power supply unit, the VCC pin is electrically connected with the output end of the VCC pin, the FB pin is electrically connected with the input end of the switch (SW 3), the GND pin is a grounding end of a chip, the CS pin is electrically connected with the input end of the switch (SW 1), and the GATE pin is electrically connected with the output end of the BUFFER (BUFFER).
  5. 5. The power control chip of claim 1, wherein the pulse generating unit outputs a pulse signal after inputting a low-level to high-level signal.
  6. 6. The power control chip of claim 5, wherein the pulse signal has a high duration of 1us.
  7. 7. The power control chip of claim 1, wherein the input of the rising edge delay unit drives the switch SW1 and the switch SW2 to be turned on after a delay x after receiving a signal from a low level to a high level.
  8. 8. The power control chip of claim 1, wherein the control terminals of the switch SW1 and the switch SW2 are turned on when a high level signal is inputted and turned off when a low level signal is inputted.
  9. 9. The power control chip of claim 1, wherein the control terminals of the switch SW3 and the switch SW4 are turned on when a high level signal is inputted and turned off when a low level signal is inputted.
  10. 10. The power control chip of claim 1, wherein the control terminals of the switch SW5 and the switch SW6 are turned on when a high level signal is inputted and turned off when a low level signal is inputted.

Description

Power control chip with variable sampling blanking time Technical Field The utility model relates to the technical field of power electronics, in particular to a power supply control chip capable of changing sampling blanking time. Background In the conventional AC-DC power conversion circuit, in the isolation solution, an isolation optocoupler and an op amp such as 431 are required to make feedback of a secondary voltage to a primary control circuit, which brings great difficulty to some cost or volume sensitive application scenarios, based on which the primary feedback-based power conversion circuit is applied, and a common circuit is shown in fig. 1, and the working and detection principle of the circuit shown in fig. 1 is as follows: The input voltage VIN is shaped by the rectifier bridge and is filtered by the output capacitor of the rectifier bridge to become direct-current voltage VBUS with slight ripple, when the MOS tube Q1 is started, the direct-current voltage VBUS charges the primary winding of the transformer, the transformer can be equivalently an inductor, and the inductor is obtained according to the charging current rule: VBUS-vcs=l (diL/dt), where VCS is the voltage of the resistor RCS, iL is the transformer primary inductor current, diL/dt is the rate of change of this current; because the resistor RCS is a small resistor, VCS cannot exceed 1V by reasonably designing the resistance range of the resistor RCS, and VBUS is 130-390 times of VCS, engineering calculation can be simplified to VBUS=L (diL/dt); When the MOS tube Q1 is turned off, the primary inductance of the transformer discharges to the secondary through turn ratio equivalence, the discharge voltage is VOUT NPS, wherein VOUT is output voltage, and NPS is the ratio of the primary turns to the secondary turns of the transformer. It is evident that the voltage of the auxiliary winding is denoted VAUX according to the principle of the transformer turn ratio, the voltage amplitude in the horizontal state at the off-time being Wherein VAUX_H is the voltage during the discharge period of the auxiliary winding inductance, VOUT and VD are the output voltage and the diode conduction voltage drop respectively,N S is the number of turns of the secondary winding; When the inductor discharges, the auxiliary winding is in a horizontal state, and after the inductor discharges, the inductor resonates with the DS of the MOS transistor Q1, so VDRAIN is reduced until the voltage of the auxiliary winding reaches VBUS, and in addition, the chip detects VAUX_H, namely the voltage of the chip sampling pin is detected by the divider resistor RU and the divider resistor RD ObviouslyIf N S, VD, RD, RU are constant for a system that has been determined, vaux_h can directly reflect the magnitude of VOUT. In practical use, as any transformer is not perfectly coupled, leakage inductance exists between the coils, when the MOS transistor Q1 is turned off, VDRAIN can vibrate due to the leakage inductance and the leakage inductance absorbing capacitance vibration, and the waveform of the VAUX can vibrate with a small amplitude, and the time and the amplitude of the vibration are in direct proportion to the energy stored in the primary side main inductance of the transformer. Obviously, the chip has to avoid the oscillation in the sampling process, and the current conventional method is that after the signal of the MOS transistor Q1 is turned off by the chip, the chip delays for a period of time to output and sample, the period of time is called as TSAMPLE_LEB, which is generally set to about 2.5us-3us, the blanking time is needed to pass through the chip to sample the partial pressure of VAUX_H, and the sampling also needs to be called as TSAMPLE, which is generally about 1 us. For the above-described process, there are two problems, specifically as follows: Firstly, when the system is in a heavy load state, as the conduction time of the MOS tube Q1 is longer, the transformer stores more energy, so that the oscillation time and the horizontal state time of VDRAIN and VAUX are long after the MOS tube Q1 is turned off, namely the state maintenance time of VAUX_H is long (the specific time is related to the load state of the system), and after the blanking time is passed, the maintenance time can be maintained for chip sampling, and related signal waveforms are shown in figure 2. However, when the load is in a light load state, the MOS tube Q1 is short in turn-on time, the energy stored by the transformer is low, but after the MOS tube Q1 is turned off by the chip, the VAUX cannot maintain the horizontal time in the time of TSAMPLE_LEB+TSAMPLE, and is in the resonance region at the end of the blanking and maintaining time period. The sampling of the chip at this time cannot reflect the actual output voltage, and the relevant waveforms are shown in fig. 3. The measured voltage is smaller than the horizontal segment, so that the chip can mistakenly take the output vol