CN-224218744-U - Display substrate, display panel and display device

CN224218744UCN 224218744 UCN224218744 UCN 224218744UCN-224218744-U

Abstract

The application discloses a display substrate, a display panel and a display device, relates to the technical field of display, and can improve the problem of film breakage so as to improve the stability of a TFT structure. The display substrate comprises a substrate layer, a first conductive layer, a semiconductor layer, a second conductive layer, a first insulating layer and a second insulating layer, wherein the second conductive layer comprises a first electrode, a second electrode and a third electrode, the first insulating layer comprises a first via hole, the second insulating layer comprises a second via hole and a third via hole, one end of the first electrode is electrically connected with one end of the semiconductor layer through the second via hole, the first electrode is electrically connected with an electrode signal wire through the first via hole, the second electrode is electrically connected with the other end of the semiconductor layer through the third via hole, the second insulating layer comprises a grid insulating structure, the grid insulating structure is positioned between the second via hole and the third via hole, the grid insulating structure comprises a first structure part, a second structure part and a third structure part, and the orthographic projection of the third structure part on the substrate layer completely covers the orthographic projection of the third electrode.

Inventors

LIU WENQU
YAO QI
ZHANG FENG
FENG XUAN
YU LIANFU
MENG DETIAN
CUI ZHAO

Assignees

京东方科技集团股份有限公司

Dates

Publication Date: 20260508
Application Date: 20250414

Claims (20)

1. A display substrate, comprising: The semiconductor device comprises a substrate layer, a first conductive layer, a semiconductor layer, a second conductive layer, a first insulating layer and a second insulating layer, wherein the first conductive layer is arranged between the substrate layer and the semiconductor layer, the semiconductor layer is arranged between the first conductive layer and the second conductive layer, the first insulating layer is arranged between the first conductive layer and the semiconductor layer, and the second insulating layer is arranged between the semiconductor layer and the second conductive layer; The first conductive layer comprises an electrode signal wire, the second conductive layer comprises a first electrode, a second electrode and a third electrode, the first insulating layer comprises a first via hole, the second insulating layer comprises a second via hole and a third via hole, the first electrode is electrically connected with one end of the semiconductor layer through the second via hole, the first electrode is electrically connected with the electrode signal wire through the first via hole, the second electrode is electrically connected with the other end of the semiconductor layer through the third via hole, and the orthographic projection of the third electrode on the substrate layer is positioned between the orthographic projections of the second via hole and the third via hole on the substrate layer; The second insulating layer comprises a gate insulating structure, the gate insulating structure is located between the second via hole and the third via hole, the gate insulating structure comprises a first structure part, a second structure part and a third structure part, the third structure part is connected between the first structure part and the second structure part, orthographic projections of the first structure part and the second structure part on the substrate layer do not overlap with orthographic projections of the third electrode on the substrate layer, orthographic projections of the third structure part on the substrate layer completely cover orthographic projections of the third electrode on the substrate layer, orthographic projections of the semiconductor layer on the substrate layer completely cover orthographic projections of the gate insulating structure on the substrate layer.
2. The display substrate of claim 1, wherein the display substrate comprises a transparent substrate, The first conductive layer comprises a shading structure; The front projection of the semiconductor layer on the substrate layer completely covers the front projection of the shading structure on the substrate layer, and/or The front projection of the shading structure on the substrate layer overlaps with the front projection of the third electrode on the substrate layer, and/or The orthographic projection of the shading structure on the substrate layer covers the orthographic projection of the first structure part on the substrate layer, or the orthographic projection of the shading structure on the substrate layer is not overlapped with the orthographic projection of the first structure part on the substrate layer, and/or The orthographic projection of the shading structure on the substrate layer overlaps with the orthographic projection of the second structure part on the substrate layer, and/or An orthographic projection of the light shielding structure on the substrate layer overlaps an orthographic projection of the third structure portion on the substrate layer.
3. The display substrate according to claim 2, wherein, The light shielding structure is electrically connected with the third electrode.
4. The display substrate according to claim 3, wherein, The light shielding structure comprises a fourth structural part, a fifth structural part and a sixth structural part, wherein the sixth structural part is connected between the fourth structural part and the fifth structural part; The orthographic projection of the sixth structure part on the substrate layer is coincident with the orthographic projection of the grid insulation structure on the substrate layer, and the orthographic projections of the fourth structure part and the fifth structure part on the substrate layer are not overlapped with the orthographic projection of the grid insulation structure on the substrate layer.
5. The display substrate of claim 1, wherein the display substrate comprises a transparent substrate, The first structure part has a dimension in the first direction of 1 μm or more, and/or The second structure portion has a dimension in the first direction of greater than or equal to 1 μm; The first direction is parallel to the plane of the semiconductor layer, and the first direction is the connecting line direction of the first electrode and the second electrode.
6. The display substrate according to any one of claims 1 to 5, wherein, The first structure part is connected with the first electrode, and the first electrode covers at least part of the edge of one end of the first structure part, which is close to the first electrode; The second insulating layer comprises a first insulating structure and a second insulating structure, the first insulating structure is positioned at the edge of one side of the second via hole away from the third electrode, and the second insulating structure is positioned at the edge of one side of the third via hole away from the third electrode; The first electrode wraps around at least a portion of an edge of the first insulating structure, and/or the second electrode wraps around at least a portion of an edge of the second insulating structure.
7. The display substrate according to claim 6, wherein, The first electrode covers the first insulating structure in a first direction with a size of less than or equal to 0.6 μm, and/or the first electrode covers the first structure in the first direction with a size of less than or equal to 0.6 μm, and/or, The second electrode coats the second insulating structure in the first direction with a size of less than or equal to 0.6 μm, and/or the second electrode coats the second structure in the first direction with a size of less than or equal to 0.6 μm; The first direction is parallel to the plane of the semiconductor layer, and the first direction is the connecting line direction of the first electrode and the second electrode.
8. The display substrate according to claim 6, wherein, The semiconductor layer comprises a fourth via hole, the fourth via hole is respectively communicated with the first via hole and the second via hole, and the first electrode is electrically connected with an electrode signal wire through the fourth via hole; Orthographic projections of the first via hole, the second via hole and the fourth via hole on the substrate layer fall into orthographic projections of the semiconductor layer on the substrate layer.
9. The display substrate of claim 8, wherein the display substrate comprises a transparent substrate, An orthographic projection of the electrode signal line on the substrate layer covers a part of the edge of one end of the semiconductor layer, which is close to the first electrode.
10. The display substrate according to any one of claims 1 to 5, wherein, The second via hole comprises a first exposed region for exposing a part of the surface of the semiconductor layer far away from the substrate layer, wherein the orthographic projection of the first exposed region on the substrate layer is not overlapped with the orthographic projection of the first electrode on the substrate layer, and/or The third via hole comprises a second exposed area, the second exposed area is used for exposing a part of the surface of one side, far away from the substrate layer, of the semiconductor layer, and orthographic projection of the second exposed area on the substrate layer is not overlapped with orthographic projection of the second electrode on the substrate layer.
11. The display substrate of claim 10, wherein the display substrate comprises a transparent substrate, The first exposed region has a dimension in the first direction of greater than or equal to 0.5 μm, and/or The second exposed region has a dimension in the first direction of greater than or equal to 0.5 μm.
12. The display substrate of claim 10, wherein the display substrate comprises a transparent substrate, The orthographic projection of the first via hole on the substrate layer is not overlapped with the orthographic projection of the semiconductor layer on the substrate layer.
13. The display substrate of claim 10, wherein the display substrate comprises a transparent substrate, Orthographic projection of the electrode signal line on the substrate layer covers orthographic projection of a part of one side of the semiconductor layer, which is close to the first electrode, on the substrate layer.
14. The display substrate of claim 10, wherein the display substrate comprises a transparent substrate, The second insulating layer comprises a first insulating structure and a second insulating structure, the first insulating structure is positioned at the edge of one side of the second via hole far away from the third electrode, the second insulating structure is positioned at the edge of one side of the third via hole far away from the third electrode, the first direction is parallel to the plane of the semiconductor layer, and the first direction is the connecting direction of the first electrode and the second electrode; the first electrode wraps at least part of the edge of the first insulating structure, and/or the second electrode wraps at least part of the edge of the second insulating structure; and/or the number of the groups of groups, The orthographic projection of the second insulating structure on the substrate layer is not overlapped with the orthographic projection of the semiconductor layer on the substrate layer.
15. The display substrate of claim 10, wherein the display substrate comprises a transparent substrate, The semiconductor layer comprises a fourth via hole, the fourth via hole is respectively communicated with the first via hole and the second via hole, and the first electrode is electrically connected with the electrode signal wire through the fourth via hole.
16. The display substrate according to claim 1, comprising: A plurality of sub-pixels arranged in an array, the sub-pixels including a pixel electrode and a driving transistor including a semiconductor layer, a first electrode, a second electrode, and a third electrode; And the grid lines are electrically connected with the driving transistors, and at least four grid lines are connected with the same row of sub-pixels.
17. The display substrate of claim 16, wherein the display substrate comprises a transparent substrate, At least one gate signal line is disposed between the light emitting regions of the n-th row of sub-pixels and the n-1 th row of sub-pixels, and/or, At least one of the gate signal lines is disposed between the light emitting regions of the n-th row of sub-pixels and the n+1-th row of sub-pixels, and/or, The at least two grid signal lines are arranged in the n-1 row sub-pixel luminous area, wherein the n-1 row sub-pixels, the n-1 row sub-pixels and the n+1 row sub-pixels are arranged in an array mode along a second direction, the second direction is the length direction of the electrode signal lines, and n is a natural number larger than 0.
18. The display substrate of claim 17, wherein the display substrate comprises a transparent substrate, The subpixels of two adjacent columns with different colors are connected with the same grid line.
19. The display substrate of claim 18, further comprising: a plurality of pixel units and a plurality of data signal transmission lines which are repeatedly arranged, wherein the data signal transmission lines are electrically connected with the data signal lines; the pixel unit comprises a plurality of sub-pixels; The subpixels of the same color in the same pixel unit are connected to the same data signal transmission line.
20. A display panel, comprising: the display substrate of any one of claims 1 to 19.

Description

Display substrate, display panel and display device Technical Field The present application relates to the field of display technologies, and in particular, to a display substrate, a display panel, and a display device. Background Currently, with the continuous development of display technology, the performance requirements of the consumer market on display products are higher and higher. However, in the process of manufacturing the display product, in the process of covering the organic insulating layer above the semiconductor layer with other film layers after etching, the film layer covering the etched organic insulating layer is easy to break due to the etching step, and the film layer break may cause oxidation of the gate, negative bias of the TFT (Thin Film Transistor ) characteristics, or conductive, so that the semiconductor device cannot pass the reliability test. In summary, how to avoid the film breakage is a problem to be solved. Disclosure of utility model The display substrate, the display panel and the display device provided by the embodiment of the application can improve the problem of film breakage so as to improve the stability of a TFT structure. In a first aspect of an embodiment of the present application, there is provided a display substrate including: The semiconductor device comprises a substrate layer, a first conductive layer, a semiconductor layer, a second conductive layer, a first insulating layer and a second insulating layer, wherein the first conductive layer is arranged between the substrate layer and the semiconductor layer, the semiconductor layer is arranged between the first conductive layer and the second conductive layer, the first insulating layer is arranged between the first conductive layer and the semiconductor layer, and the second insulating layer is arranged between the semiconductor layer and the second conductive layer; The first conductive layer comprises an electrode signal wire, the second conductive layer comprises a first electrode, a second electrode and a third electrode, the first insulating layer comprises a first via hole, the second insulating layer comprises a second via hole and a third via hole, the first electrode is electrically connected with one end of the semiconductor layer through the second via hole, the first electrode is electrically connected with the electrode signal wire through the first via hole, the second electrode is electrically connected with the other end of the semiconductor layer through the third via hole, and the orthographic projection of the third electrode on the substrate layer is positioned between the orthographic projections of the second via hole and the third via hole on the substrate layer; The second insulating layer comprises a gate insulating structure, the gate insulating structure is located between the second via hole and the third via hole, the gate insulating structure comprises a first structure part, a second structure part and a third structure part, the third structure part is connected between the first structure part and the second structure part, orthographic projections of the first structure part and the second structure part on the substrate layer do not overlap with orthographic projections of the third electrode on the substrate layer, orthographic projections of the third structure part on the substrate layer completely cover orthographic projections of the third electrode on the substrate layer, orthographic projections of the semiconductor layer on the substrate layer completely cover orthographic projections of the gate insulating structure on the substrate layer. In some embodiments, the first conductive layer includes a light shielding structure; The front projection of the semiconductor layer on the substrate layer completely covers the front projection of the shading structure on the substrate layer, and/or The front projection of the shading structure on the substrate layer overlaps with the front projection of the third electrode on the substrate layer, and/or The orthographic projection of the shading structure on the substrate layer covers the orthographic projection of the first structure part on the substrate layer, or the orthographic projection of the shading structure on the substrate layer is not overlapped with the orthographic projection of the first structure part on the substrate layer, and/or The orthographic projection of the shading structure on the substrate layer overlaps with the orthographic projection of the second structure part on the substrate layer, and/or An orthographic projection of the light shielding structure on the substrate layer overlaps an orthographic projection of the third structure portion on the substrate layer. In some embodiments, the light shielding structure is electrically connected to the third electrode. In some embodiments, the light shielding structure includes a fourth structural portion, a fifth structural portion, and a sixth st