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CN-224218783-U - Memristor with micro-nano interlocking interface

CN224218783UCN 224218783 UCN224218783 UCN 224218783UCN-224218783-U

Abstract

The utility model belongs to the technical field of semiconductor memristors, and relates to a memristor with a micro-nano interlocking interface, which comprises a substrate layer, a bottom electrode layer, a charge compensation dielectric layer, a semiconductor active layer and a top electrode layer; the junction surface of the semiconductor active layer and the charge compensation dielectric layer is provided with a micro-nano structure, and physical interlocking is formed between the two layers through the micro-nano structure. The micro-nano interlocking structure is used for restricting an ion migration path through a physical anchoring effect, keeping consistency and repeatability of electrical behaviors in multiple cycles, improving structural stability and service life of a device, and dispersing bending stress to the side wall of the microstructure through the interlocking interface to effectively prevent interlayer peeling.

Inventors

  • ZHANG ZHONGDA
  • WANG SUIDONG

Assignees

  • 苏州大学

Dates

Publication Date
20260508
Application Date
20260408

Claims (10)

  1. 1. Memristor with micro-nano interlock interface, characterized by comprising: A substrate layer; a bottom electrode layer provided on an upper surface of the substrate layer; a charge compensation dielectric layer disposed on an upper surface of the bottom electrode layer; the semiconductor active layer is arranged on the upper surface of the charge compensation dielectric layer, and the junction surface of the semiconductor active layer and the charge compensation dielectric layer is provided with a micro-nano structure, and physical interlocking is formed between the semiconductor active layer and the charge compensation dielectric layer through the micro-nano structure; and a top electrode layer disposed on an upper surface of the semiconductor active layer.
  2. 2. The memristor with a micro-nano interlocking interface of claim 1, wherein the micro-nano structure is a saw tooth texture comprising alternately connected first teeth and first recesses formed on the charge compensation dielectric layer surface, and second teeth and second recesses formed alternately connected with the semiconductor active layer surface, the first teeth being embedded in the second recesses, the second teeth being embedded in the first recesses.
  3. 3. The memristor with the micro-nano interlocking interface of claim 2, wherein the first tooth or/and the second tooth is a triangular tooth, the first recess is adapted to the second tooth profile, and the second recess is adapted to the first tooth profile.
  4. 4. The memristor with micro-nano interlocking interface of claim 3, wherein the triangular tooth has an inclined sidewall, and an included angle between the sidewall and a horizontal upper surface of the charge compensation dielectric layer is 30 ° to 60 °.
  5. 5. The memristor with a micro-nano interlocking interface of claim 1, wherein the charge compensation dielectric layer has a thickness of 30 nm-200 nm.
  6. 6. The memristor with micro-nano interlocking interface of claim 1 or 5, wherein a thickness ratio of the charge compensation dielectric layer to the semiconductor active layer is 1:1 to 5:1.
  7. 7. The memristor with a micro-nano interlocking interface of claim 1, wherein the micro-nano structure has a cross-sectional shape of a wavy or trapezoidal wave shape, which is slit in a thickness direction of the memristor.
  8. 8. The memristor with micro-nano interlocking interface of claim 1, wherein the top electrode layer is comprised of a plurality of interconnected mesh cells with stress relief gaps between adjacent mesh cells.
  9. 9. The memristor with micro-nano interlock interface of claim 8, wherein the mesh cells are hexagonal or honeycomb.
  10. 10. The memristor with micro-nano interlocking interface of claim 1 or 8, wherein the thickness of the top electrode layer is 30 nm-200 nm.

Description

Memristor with micro-nano interlocking interface Technical Field The utility model relates to the technical field of semiconductor memristors, in particular to a memristor with a micro-nano interlocking interface. Background With the rapid development of neuromorphic computation and brain-like intelligent hardware, the development of a hardware base unit capable of simulating the plasticity and memory functions of biological synapses has become an industry core resort. Memristors, which are stimulus-dependent circuit elements of a two-terminal structure, are considered as key physical components for constructing artificial neural networks because of their highly analogous electrical properties to biological synapses. Particularly, the memristor constructed based on the polymer material has good biocompatibility, is expected to realize continuous regulation and control of resistance through interface ion doping effect, and provides an important direction for physical realization of the flexible brain-like chip. However, the existing memristor technology faces a biggest problem in practical application, namely, the memristor mostly adopts a metal-functional layer-metal sandwich structure, and the working principle of the memristor mainly depends on a conductive filament mechanism. In the case of an active metal such as silver or aluminum for the top electrode, the action of the electric field causes metal ions to precipitate and form metal filaments in the dielectric layer that extend through the upper and lower electrodes. This mechanism of operation has inherent drawbacks: Firstly, from the physical mechanism, the formation and fracture of the conductive filaments in the dielectric layer have great randomness, and the resistance state of the memristor presents nonlinear step jump, namely the current discretization phenomenon is serious because the precipitation sites and the growth paths of metal ions cannot be precisely controlled. The randomness makes the memristor difficult to realize fine continuous resistance adjustment, and the core requirements of nerve morphology calculation on polymorphic storage and synaptic weight linear updating cannot be met. Second, because the filament growth position is not fixed, conductive filament formation and fusing occur at different locations of the dielectric layer during each cycle operation, and this uncontrolled physical process can result in cumulative physical damage to the dielectric layer. With the increase of the circulation times, irreversible structural damage is gradually formed inside the dielectric layer, so that the reproducibility and the service life of the memristor are reduced. More critical is that the metal filaments are brittle physical bonds in nature, whose mechanical properties are fundamentally mismatched with the flexible substrate. When the memristor is applied to wearable equipment or flexible display and other scenes to bear bending stress, the filaments penetrating through the dielectric layer are extremely easy to physically break, so that the memristor is invalid, and the defect fundamentally limits the application prospect of the memristor in the emerging fields of wearable equipment, flexible display and the like. Disclosure of utility model The memristor with the micro-nano interlocking interface is provided, and a physical interlocking is formed through the micro-nano structure of the joint surface of the semiconductor active layer and the charge compensation medium layer, so that a planar ion migration mechanism is realized to replace a punctiform conductive filament, and the mechanical flexibility and bending resistance of the memristor are enhanced through the stress dispersion effect of the interlocking interface while the resistance regulation linearity and the electrical stability are improved. In order to solve the technical problems, the utility model provides a memristor with a micro-nano interlocking interface, comprising: A substrate layer; a bottom electrode layer provided on an upper surface of the substrate layer; a charge compensation dielectric layer disposed on an upper surface of the bottom electrode layer; the semiconductor active layer is arranged on the upper surface of the charge compensation dielectric layer, and the junction surface of the semiconductor active layer and the charge compensation dielectric layer is provided with a micro-nano structure, and physical interlocking is formed between the semiconductor active layer and the charge compensation dielectric layer through the micro-nano structure; and a top electrode layer disposed on an upper surface of the semiconductor active layer. Preferably, the micro-nano structure is a zigzag texture, and comprises first teeth and first concave parts which are formed on the surface of the charge compensation medium layer and are alternately connected, and second teeth and second concave parts which are formed on the surface of the semiconductor active layer and a