CN-224218806-U - Packaging structure of chip carrier plate

CN224218806UCN 224218806 UCN224218806 UCN 224218806UCN-224218806-U

Abstract

A packaging structure of a chip carrier comprises the chip carrier and a hard frame. The hard frame is arranged on the outer frame of the chip carrier plate through the bonding layer. The chip carrier comprises a substrate, a plurality of ceramic plates, a plurality of metal columns, a resin layer, a first circuit layer and a second circuit layer. The substrate is provided with a first through hole penetrating through the upper surface and the lower surface. The ceramic plate is provided with a second through hole penetrating through the first surface and the second surface. The metal column is filled in the second through hole. The resin layer covers the upper surfaces of the ceramic plate and the substrate, and is provided with openings corresponding to the second through holes. The first circuit layer is positioned on a part of the surface of the resin layer and in the opening and is connected with the metal column. The second circuit layer is positioned in a part of the lower surface of the substrate and the first through hole and is connected with the metal column.

Inventors

LIN DINGHAO
ZHANG QIAOZHENG
Lin Zhouying
ZHANG QIANWEI

Assignees

景硕科技股份有限公司

Dates

Publication Date: 20260508
Application Date: 20250414

Claims (8)

1. A package structure of a chip carrier, comprising: A chip carrier, comprising: A substrate, including an upper surface and a lower surface, the substrate having a plurality of first through holes penetrating the upper surface and the lower surface; The ceramic plates are arranged on the upper surface of the substrate, a plurality of second through holes are formed in the ceramic plates, and a first surface and a second surface of each ceramic plate are penetrated through the ceramic plates respectively; A plurality of metal posts respectively filled in the second through holes; The resin layer is positioned on the upper surface of the substrate and the ceramic plates and covers the ceramic plates and the upper surface of the substrate, and is provided with a plurality of openings which respectively correspond to the second through holes; A first circuit layer disposed on a part of a surface of the resin layer and in the openings and connected with the metal posts, and A second circuit layer disposed on a part of the lower surface of the substrate and in the first through holes and connected with the metal posts, and And the hard frame is arranged on the outer frame of the chip carrier plate through an adhesive layer.
2. The package structure of a chip carrier as set forth in claim 1, wherein: The chip carrier plate comprises an invalid area, and the invalid area is positioned at the outer periphery of the chip carrier plate.
3. The package structure of a chip carrier as claimed in claim 2, wherein: The hard frame comprises two first brackets and two second brackets, wherein the two first brackets are arranged in parallel, the two second brackets are arranged in parallel, and two ends of the hard frame are respectively connected with the two first brackets, and the hard frame is integrally formed.
4. The package structure of a chip carrier as claimed in claim 2, wherein: The hard frame comprises two first brackets and two second brackets, wherein the two first brackets are arranged in parallel, the two second brackets are arranged in parallel, and two ends of the hard frame are respectively assembled with the two first brackets.
5. The package structure of a chip carrier according to any one of claims 3 or 4, wherein: The hard frame further comprises a plurality of abutting parts, the abutting parts extend out of the hard frame and are respectively abutted against the ineffective area of the chip carrier plate.
6. The package structure of a chip carrier as claimed in claim 5, wherein: the plurality of abutting parts extend from the first brackets and the second brackets respectively.
7. The package structure of a chip carrier as claimed in claim 5, wherein: the plurality of abutting parts are respectively positioned at the joint of each first bracket and each second bracket.
8. The package structure of a chip carrier as set forth in claim 1, wherein: The thickness of the ceramic plate is 200 to 1000 μm, and the height of the hard frame is greater than the thickness of the chip carrier plate.

Description

Packaging structure of chip carrier plate Technical Field Relates to the field of chip packaging, in particular to a packaging structure of a chip carrier plate. Background With the development of various chips, chips with various sizes and different pin gaps are mounted on one circuit board, so that the semiconductor package is led into an intermediate board, the size of the circuit board can be simplified, and the circuit board is soldered after different chips are mounted through the intermediate board. For the requirement of criss-cross large-area stitching, the biggest challenges include thickness, flatness, and thermal stability of the chip carrier. At present, ceramic plates are introduced as cores or other hard substrates to solve the problems of thickness, flatness and thermal stability. However, since the ceramic board is also typically laminated, redistribution of the circuit is performed. The redistribution layer is typically formed on the resin layer, and may overheat and deform when the resin layer is used for a long period of time. This may lead to detachment of the weld, resulting in electrical defects. Disclosure of utility model A packaging structure of a chip carrier is provided. The packaging structure of the chip carrier comprises the chip carrier and a hard frame. The hard frame is arranged on the outer frame of the chip carrier plate through the bonding layer. The chip carrier includes a substrate, a plurality of ceramic plates, a plurality of metal posts, a resin layer, a first circuit layer, and a second circuit layer. The substrate comprises an upper surface and a lower surface, and a plurality of first through holes penetrating through the upper surface and the lower surface are formed in the substrate. The ceramic plate is arranged on the upper surface of the substrate, a plurality of second through holes are formed in the ceramic plate, and the second through holes penetrate through the first surface and the second surface of each ceramic plate respectively. The metal posts are respectively filled in the second through holes. The resin layer is positioned on the upper surface of the substrate and the ceramic plate, covers the ceramic plate and the upper surface of the substrate, and is provided with a plurality of openings which respectively correspond to the second through holes. The first circuit layer is positioned on a part of the surface of the resin layer and in the opening and is connected with the metal column. The second circuit layer is positioned in a part of the lower surface of the substrate and the first through hole and is connected with the metal column. In some embodiments, the chip carrier includes an inactive area located at an outer periphery of the chip carrier. In more detail, in some embodiments, the hard frame includes two first brackets and two second brackets, the two first brackets are arranged in parallel, the two second brackets are arranged in parallel, and two ends of the hard frame are respectively connected with the two first brackets, wherein the hard frame is integrally formed. In more detail, in some embodiments, the hard frame includes two first brackets and two second brackets, the two first brackets are arranged in parallel, the two second brackets are arranged in parallel, and two ends of the hard frame are respectively assembled with the two first brackets. Further, in some embodiments, the hard frame further includes a plurality of abutting portions, which extend from the hard frame and respectively abut against the inactive areas of the chip carrier. In more detail, in some embodiments, the abutment extends from each first bracket and each second bracket, respectively. In more detail, in some embodiments, the abutments are respectively located at the junctions of the first brackets and the second brackets. In some embodiments, the thickness of the ceramic plate is 200 to 1000 μm and the height of the rigid frame is greater than the thickness of the chip carrier plate. As described in the foregoing embodiments, the rigid frame is used to limit the chip carrier, so as to limit the shrinkage and expansion of the chip carrier, reduce the deformation that may occur, and provide heat dissipation, further maintain the thermal stability of the chip carrier, and improve the service life of the whole product. Drawings FIG. 1 is an exploded view of a first embodiment of a package structure for a chip carrier; FIG. 2 is a partial cross-sectional view of a first embodiment of a package structure of a chip carrier; fig. 3 is a perspective view of a second embodiment of a package structure of a chip carrier; Fig. 4 is a perspective view of a third embodiment of a package structure of a chip carrier, and Fig. 5 is a perspective view of a fourth embodiment of a package structure of a chip carrier. [ Symbolic description ] 1 Chip carrier plate 10 Substrate 10A upper surface 10B lower surface 11 First through hole 15 Ineffective area 20 Ceramic plate 20A