CN-224218811-U - Packaging structure

Abstract

The utility model provides a packaging structure which is applied to the technical field of semiconductor packaging. In the utility model, the first chip is mounted in advance, so that the first packaging layer can be pressed in front when the first dielectric layer is formed by lamination, namely, the first chip is prevented from being damaged, the packaging difficulty and the packaging cost can be reduced, the first dielectric layer can be laminated on the first packaging layer, and the second dielectric layer can be laminated on the second surface (the surface without the first packaging layer) of the first substrate at the same time, the first dielectric layer and the second dielectric layer which are made of thermosetting resin can be utilized, and the stress redistribution and the stress counteracting can be realized under uniform pressure in the heat curing process, thereby achieving the purpose of improving the warpage.

Inventors

• WANG ZHINAN
• Jiang Pinfang

Assignees

• 唯捷创芯(天津)电子技术股份有限公司

Dates

Publication Date

20260508

Application Date

20250528

Claims (10)

1. 1. A package structure, comprising: a first substrate having a first surface and a second surface disposed opposite to each other; a first metal layer disposed on a first surface of the first substrate; The first packaging layer is arranged on the first metal layer and comprises at least one first chip embedded in the first packaging layer, and a first gap is reserved between the first chip and the first metal layer; the second metal layer is arranged on the first packaging layer and is provided with a second gap with the first chip; the first dielectric layer is arranged on the second metal layer; And the third metal layer is arranged on the second surface of the first substrate.
2. 2. The package structure of claim 1, further comprising: and the second dielectric layer is arranged on the third metal layer.
3. 3. The package structure of claim 2, further comprising: the fourth metal layer is arranged on the first dielectric layer; and the second packaging layer is positioned on the fourth metal layer.
4. 4. The package structure of claim 2, further comprising: At least one first conductive post is positioned in the first substrate and directly contacts the first metal layer and/or the third metal layer on the first substrate through the first substrate.
5. 5. The package structure of claim 1, further comprising: The second conductive column is positioned in the first packaging layer at least on one side of the first chip and directly contacts with the first metal layer and the second metal layer through the first packaging layer.
6. 6. The package structure of claim 1, further comprising: And the at least one solder ball is positioned in the first packaging layer at least on one side of the first chip and directly contacts with the first metal layer and the second metal layer through the first packaging layer.
7. 7. The package structure of claim 3, further comprising: At least one third conductive post is arranged in the first dielectric layer and/or the second dielectric layer, passes through the first dielectric layer and/or the second dielectric layer and is in direct contact with the second metal layer, the fourth metal layer and/or the third metal layer.
8. 8. The package structure of claim 1, further comprising: And the plurality of bumps or the plurality of welding spots are positioned in the first gap or the second gap so as to mount the first chip in the first packaging layer.
9. 9. The package structure of claim 2, wherein the material of the first dielectric layer and/or the second dielectric layer comprises a thermosetting resin.
10. 10. The package structure of claim 3, further comprising: The second chip is arranged in the second packaging layer.

Description

Packaging structure Technical Field The utility model relates to the technical field of semiconductors, in particular to a packaging structure. Background With the rapid development of 5G/6G communication, fan-out WAFER LEVEL PACKAGE (FOWLP) package structures are widely used in the semiconductor industry. The single chip is cut from the wafer and then is reversely packaged on a carrier wafer, the main advantages are high density integration, small size of a packaged product, excellent product performance, high signal transmission frequency and the like, the fan out technology mainly realizes multi-pin output and smaller output pin spacing, the conventional double-sided packaged product structure or fan-out packaged product structure mainly forms a packaging structure on the front side and the back side of the same substrate, the wiring density of the substrate is limited due to the fact that the same substrate is adopted for plastic packaging, the wiring requirement of higher density cannot be met, and the packaging is carried out on two sides of the single substrate, the substrate support is poor, the other side is processed after one side is finished, and the warping problem is easy to occur. Disclosure of utility model The utility model aims to provide a packaging structure which is used for improving wiring density, reducing packaging process and improving the number of stacked chips, and finally reducing the risk of warping and packaging cost. In order to solve the above technical problems, the present utility model provides a packaging structure, including: a first substrate having a first surface and a second surface disposed opposite to each other; a first metal layer disposed on a first surface of the first substrate; The first packaging layer is arranged on the first metal layer and comprises at least one first chip embedded in the first packaging layer, and a first gap is reserved between the first chip and the first metal layer; the second metal layer is arranged on the first packaging layer and is provided with a second gap with the first chip; the first dielectric layer is arranged on the second metal layer. Optionally, the package structure may further include: a third metal layer disposed on the second surface of the first substrate; and the second dielectric layer is arranged on the third metal layer. Optionally, the package structure may further include: the fourth metal layer is arranged on the first dielectric layer; and the second packaging layer is positioned on the fourth metal layer. Optionally, the package structure may further include: At least one first conductive post is positioned in the first substrate and directly contacts the first metal layer and/or the third metal layer on the first substrate through the first substrate. Optionally, the package structure may further include: The second conductive column is positioned in the first packaging layer at least on one side of the first chip and directly contacts with the first metal layer and the second metal layer through the first packaging layer. Optionally, the package structure may further include: And the at least one solder ball is positioned in the first packaging layer at least on one side of the first chip and directly contacts with the first metal layer and the second metal layer through the first packaging layer. Optionally, the package structure may further include: At least one third conductive post is arranged in the first dielectric layer and/or the second dielectric layer, passes through the first dielectric layer and/or the second dielectric layer and is in direct contact with the second metal layer, the fourth metal layer and/or the third metal layer. Optionally, the package structure may further include: And the plurality of bumps or the plurality of welding spots are positioned in the first gap or the second gap so as to mount the first chip in the first packaging layer. The material of the first dielectric layer and/or the second dielectric layer comprises a thermosetting resin. Optionally, the package structure may further include: The second chip is arranged in the second packaging layer. As described above, in the package structure provided by the present utility model, a single-sided package may be first performed on a first substrate, for example, a first package layer having a first chip disposed therein may be formed on a first surface of the first substrate, and then at least one dielectric layer, for example, a first dielectric layer may be laminated on the first package layer, which has the unexpected effect that, since the first chip is mounted in advance, the first package layer may be subjected to front-side pressure during lamination to form the first dielectric layer, i.e., the first chip may be prevented from being damaged, and the package difficulty and cost may be reduced, and a second dielectric layer may be laminated on a second surface (surface on which the first package layer is not for