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CN-224218818-U - Chip packaging structure and electronic equipment

CN224218818UCN 224218818 UCN224218818 UCN 224218818UCN-224218818-U

Abstract

The application discloses a chip packaging structure and electronic equipment, which comprises a packaging substrate, a bare chip, a protection ring and a reinforcing ring, wherein the bare chip is fixed on the packaging substrate and is electrically connected with the packaging substrate, the protection ring is fixed on the packaging substrate, the protection ring is arranged around the bare chip, the reinforcing ring is fixed on the packaging substrate, the reinforcing ring is arranged around the bare chip, and at least part of the reinforcing ring is positioned between the protection ring and the packaging substrate, so that the warping of the chip packaging structure can be reduced through the reinforcing ring, and the area of the packaging substrate additionally occupied by the reinforcing ring can be reduced through the positioning of at least part of the reinforcing ring between the protection ring and the packaging substrate, and the integration level of the chip packaging structure is improved.

Inventors

  • CHEN SONGJIAO
  • WU JIAJIN

Assignees

  • 飞腾信息技术有限公司

Dates

Publication Date
20260508
Application Date
20250610

Claims (10)

  1. 1. A chip package structure, comprising: packaging a substrate; a die fixed on the package substrate and electrically connected with the package substrate; A guard ring fixed on the package substrate, the guard ring disposed around the die; The reinforcing ring is fixed on the packaging substrate, the reinforcing ring is arranged around the bare chip, and at least part of the reinforcing ring is positioned between the protecting ring and the packaging substrate.
  2. 2. The chip package structure of claim 1, wherein the stiffener ring comprises a first sub stiffener ring and a second sub stiffener ring; The protection ring comprises a first sub protection ring and a second sub protection ring, wherein the first sub protection ring is positioned between the first sub reinforcement ring and the packaging substrate, and the second sub reinforcement ring is positioned between the bare chip and the second sub protection ring.
  3. 3. The chip package structure of claim 2, wherein the first sub-guard ring and the first sub-stiffener ring have the same direction of extension as the short side of the die, and the second sub-guard ring and the second sub-stiffener ring have the same direction of extension as the long side of the die.
  4. 4. The chip package structure of claim 2, wherein the distance between the second sub-stiffener ring and the die and the distance between the second sub-stiffener ring and the second sub-guard ring are both greater than 0.5mm.
  5. 5. The chip package structure of claim 1, further comprising a package cover plate thermally coupled to a side of the die facing away from the package substrate, the package cover plate being fixedly coupled to a side of the guard ring facing away from the package substrate.
  6. 6. The chip package structure of claim 1, further comprising a heat spreader thermally coupled to a side of the die facing away from the package substrate, the heat spreader being fixedly coupled to the package substrate.
  7. 7. The chip package structure according to claim 1, wherein a part of the reinforcing ring is located between the guard ring and the package substrate, a groove is provided on a side of the guard ring facing the package substrate, a part of the reinforcing ring is located in the groove and fixedly connected with an inner wall of the groove, or All the reinforcing rings are positioned between the protection ring and the packaging substrate, and one side of the reinforcing rings facing the packaging substrate is fixedly connected with one side of the protection ring away from the packaging substrate.
  8. 8. The chip package structure of claim 1, wherein the material of the stiffener ring comprises a stainless steel material with a nickel plated surface or a copper material with a nickel plated surface.
  9. 9. The chip package structure of claim 1, wherein the width of the stiffener ring ranges from 2mm to 6mm, and the thickness of the stiffener ring ranges from 0.3mm to 3mm.
  10. 10. An electronic device comprising the chip package structure of any one of claims 1-9.

Description

Chip packaging structure and electronic equipment Technical Field The present application relates to the field of chip technologies, and in particular, to a chip packaging structure and an electronic device. Background Current chip package structures include a package substrate and a die attached to the package substrate. However, as the integration level of the chip is higher and higher, the number of dies fixed on the package substrate is higher and higher, which results in greater and greater warpage of the chip package structure. Disclosure of utility model The application discloses a chip packaging structure and electronic equipment, which are used for solving the problem that the warpage of the chip packaging structure is larger and larger along with the higher and higher integration level of a chip. In a first aspect, the application discloses a chip packaging structure, which comprises a packaging substrate, a bare chip, a protection ring and a reinforcing ring, wherein the bare chip is fixed on the packaging substrate and is electrically connected with the packaging substrate, the protection ring is fixed on the packaging substrate and is arranged around the bare chip, the reinforcing ring is fixed on the packaging substrate and is arranged around the bare chip, and at least part of the reinforcing ring is positioned between the protection ring and the packaging substrate. In this way, not only the warpage of the chip package structure can be reduced by the stiffener ring, but also the area of the package substrate additionally occupied by the stiffener ring can be reduced by having at least part of the stiffener ring between the guard ring and the package substrate, and the integration level of the chip package structure can be improved. In some embodiments of the application, the stiffener ring includes a first sub-stiffener ring and a second sub-stiffener ring, the guard ring includes a first sub-guard ring and a second sub-guard ring, the first sub-guard ring is located between the first sub-stiffener ring and the package substrate, and the second sub-stiffener ring is located between the die and the second sub-guard ring. In this way, the warpage of the chip package structure can be suppressed to the maximum on the basis of improving the integration level of the chip package structure. In some embodiments of the present application, the first sub-guard ring and the first sub-stiffener ring have the same direction of extension as the short side of the die, and the second sub-guard ring and the second sub-stiffener ring have the same direction of extension as the long side of the die. Since the warpage in the extending direction of the long side of the die is larger than the warpage in the extending direction of the short side of the die, the warpage of the chip package structure can be suppressed to the maximum extent on the basis of improving the integration level of the chip package structure. In some embodiments of the application, the distance between the second sub-stiffener ring and the die and the distance between the second sub-stiffener ring and the second sub-guard ring are both greater than 0.5mm. In this way, by reasonably setting the positional relationship of the second sub stiffener ring with the die and the second sub guard ring, the stiffener ring can be made to achieve the best warpage-suppressing effect. In some embodiments of the present application, the chip package structure further includes a package cover, where the package cover is thermally connected to a side of the die facing away from the package substrate, and the package cover is fixedly connected to a side of the guard ring facing away from the package substrate. In this way, the packaging cover plate and the protection ring can form a packaging cover shell, so that the chip packaging structure can be suitable for equipment with low requirements on thickness. In some embodiments of the present application, the chip package structure further includes a heat spreader, where the heat spreader is thermally connected to a side of the die facing away from the package substrate, and the heat spreader is fixedly connected to the package substrate. In this way, the thickness of the chip package structure can be made smaller, so that the chip package structure can be applied to a device having a high thickness requirement. In some embodiments of the present application, a part of the reinforcing ring is located between the protecting ring and the packaging substrate, a groove is formed on a side, facing the packaging substrate, of the protecting ring, a part of the reinforcing ring is located in the groove and is fixedly connected with an inner wall of the groove, or all of the reinforcing ring is located between the protecting ring and the packaging substrate, and all of the reinforcing ring is fixedly connected with a side, facing the packaging substrate, of the protecting ring, facing away from the packaging substrate.