CN-224231910-U - Fault monitoring circuit, chip and vehicle

Abstract

The application is suitable for the technical field of fault monitoring and provides a fault monitoring circuit, a chip and a vehicle. The fault monitoring circuit comprises a monitoring module, a first logic module, a second logic module, a first delay module and a second delay module, wherein the second delay module is respectively and electrically connected with the first logic module and the second logic module, the first logic module is used for being electrically connected with the output end of the prokaryote, the input end of the monitoring module is electrically connected with the input end of the prokaryote through the first delay module, and the output end of the monitoring module is electrically connected with the second logic module. The fault monitoring circuit provided by the embodiment of the application can realize the monitoring of the prokaryote, and if the second logic module outputs a logic monitoring signal, the second logic module indicates that the monitoring signal is different from the initial signal, and the abnormal state of the nuclear inspection is represented. When the fault monitoring is carried out on the prokaryotic, the fault monitoring circuit can rapidly determine that the core inspection is abnormal through the logic monitoring signal, and the monitoring response speed when the CPU core fails is obviously improved.

Inventors

• CAO CHANGFENG
• WANG JUNWEI

Assignees

• 湖南紫荆半导体有限公司

Dates

Publication Date

20260512

Application Date

20250430

Claims (10)

1. 1. The fault monitoring circuit is characterized by comprising a monitoring module, a first logic module, a second logic module, a first delay module and a second delay module, wherein the second delay module is respectively and electrically connected with the first logic module and the second logic module, the first logic module is used for being electrically connected with a prokaryotic output end, an input end of the monitoring module is electrically connected with the prokaryotic input end through the first delay module, and an output end of the monitoring module is electrically connected with the second logic module; The first delay module is used for delaying an input signal for a preset time and then transmitting the delayed input signal to the monitoring module, the monitoring module is used for outputting a monitoring signal to the second logic module according to the input signal, the first logic module is used for outputting a first logic signal according to an initial signal, the initial signal is a signal output by the prokaryote according to the input signal, the second delay module is used for delaying the first logic signal for the preset time to obtain a second delay signal, transmitting the second delay signal to the second logic module, and the second logic module is used for outputting a logic monitoring signal according to the monitoring signal and the second delay signal.
2. 2. The fault monitoring circuit of claim 1, wherein the monitoring module comprises a monitoring core electrically connected to the first delay module and the second logic module, respectively.
3. 3. The fault monitoring circuit of claim 1, wherein the first logic module comprises a not gate having an input for electrical connection with the output of the core, the output of the not gate being electrically connected with the second delay module.
4. 4. The fault monitoring circuit of claim 1, wherein the second logic module comprises an exclusive nor gate, a first input of the exclusive nor gate is electrically connected to the second delay module, a second input of the exclusive nor gate is electrically connected to the monitoring module, and an output of the exclusive nor gate is configured to output the logic monitoring signal.
5. 5. The fault monitoring circuit of claim 1, wherein the first delay module comprises a first delay having an input for receiving the input signal, an output of the first delay being electrically connected to the monitoring module.
6. 6. The fault monitoring circuit of claim 1, wherein the second delay module comprises a second delay, an input of the second delay is electrically connected to the first logic module, and an output of the second delay is electrically connected to the second logic module.
7. 7. The fault monitoring circuit of any one of claims 1-6, further comprising a third logic module and a fourth logic module, the third logic module being electrically connected to the prokaryotic and the first logic module, respectively, the fourth logic module being electrically connected to the monitoring module and the second logic module, respectively; The third logic module is used for outputting a third logic signal to the first logic module according to the initial signal, and the fourth logic module is used for outputting a fourth logic signal to the second logic module according to the monitoring signal.
8. 8. The fault monitoring circuit of any one of claims 1-6, further comprising a memory module electrically coupled to the second logic module, the memory module configured to store the logic monitoring signal.
9. 9. A chip comprising the fault monitoring circuit of any one of claims 1-8.
10. 10. A vehicle comprising the chip of claim 9.

Description

Fault monitoring circuit, chip and vehicle Technical Field The application belongs to the technical field of fault monitoring, and particularly relates to a fault monitoring circuit, a chip and a vehicle. Background With the development of integrated circuit technology, a CPU (Central Processing Unit ) core inside a chip plays a critical role in various electronic devices. The CPU core is a core component of the chip and is responsible for executing calculation and control tasks. However, various failures such as logic errors, timing errors, power supply fluctuations, etc. of the CPU core may occur due to manufacturing defects, environmental factors, and aging caused by long-term use. These faults not only affect the normal operation of the system, but also may cause data loss, system crashes and even potential safety hazards. Therefore, the CPU core is monitored in real time, faults are detected and processed in time, and the method is important for improving the reliability and stability of chips and systems. However, existing monitoring of the CPU core generally employs a monitoring timer, and the running state of the CPU core is monitored by setting a time threshold. If the CPU core does not reset the monitoring timer within the specified time, the CPU core is indicated to possibly have faults. However, the adoption of the monitoring timer can trigger the reset signal by taking a certain time, so that the response speed is slower when the CPU core fails. Disclosure of utility model The embodiment of the application provides a fault monitoring circuit, a chip and a vehicle, which can solve the problem that the response speed is low when a CPU core fails by adopting a monitoring timer in the conventional fault monitoring method. In a first aspect, an embodiment of the present application provides a fault monitoring circuit, including a monitoring module, a first logic module, a second logic module, a first delay module and a second delay module, where the second delay module is electrically connected with the first logic module and the second logic module, the first logic module is electrically connected with a prokaryotic output end, an input end of the monitoring module is electrically connected with the prokaryotic input end through the first delay module, and an output end of the monitoring module is electrically connected with the second logic module; The first delay module is used for delaying an input signal for a preset time and then transmitting the delayed input signal to the monitoring module, the monitoring module is used for outputting a monitoring signal to the second logic module according to the input signal, the first logic module is used for outputting a first logic signal according to an initial signal, the initial signal is a signal output by the prokaryote according to the input signal, the second delay module is used for delaying the first logic signal for the preset time to obtain a second delay signal, transmitting the second delay signal to the second logic module, and the second logic module is used for outputting a logic monitoring signal according to the monitoring signal and the second delay signal. In a possible implementation manner of the first aspect, the monitoring module includes a monitoring core, and the monitoring core is electrically connected to the first delay module and the second logic module respectively. In a possible implementation manner of the first aspect, the first logic module includes an inverter, an input end of the inverter is used for being connected with the primary power, and an output end of the inverter is electrically connected with the second delay module. In a possible implementation manner of the first aspect, the second logic module includes an exclusive-or gate, a first input terminal of the exclusive-or gate is electrically connected to the second delay module, a second input terminal of the exclusive-or gate is electrically connected to the monitoring module, and an output terminal of the exclusive-or gate is used for outputting the logic monitoring signal. In a possible implementation manner of the first aspect, the first delay module includes a first delay, an input end of the first delay is used for receiving the input signal, and an output end of the first delay is electrically connected with the monitoring module. In a possible implementation manner of the first aspect, the second delay module includes a second delay, an input end of the second delay is electrically connected to the first logic module, and an output end of the second delay is electrically connected to the second logic module. In a possible implementation manner of the first aspect, the fault monitoring circuit further includes a third logic module and a fourth logic module, where the third logic module is electrically connected to the prokaryotic and the first logic module, and the fourth logic module is electrically connected to the monitoring module and the second l