CN-224231911-U - KGD high temperature test system

Abstract

The application discloses a KGD high-temperature test system, which comprises a test socket, wherein a test loop and a discharge loop are connected in parallel on the test socket, the test loop and the discharge loop are connected to the test socket through a relay, and the relay controls the test socket to be respectively communicated with the test loop or the discharge loop. The test socket solves the problems that the conventional test loop has larger noise and current limiting optimization, the test loop does not perform current limiting optimization, so that the test causes thermal breakdown of a chip and causes damage to the test socket, the test efficiency and the reliability of the chip test are improved, and the maintenance cost of the test socket is reduced.

Inventors

• HUANG JUNJIE
• DING LI

Assignees

• 江苏昕感科技有限责任公司

Dates

Publication Date

20260512

Application Date

20250509

Claims (7)

1. 1. The utility model provides a KGD high temperature test system which characterized in that, includes test socket, connect in parallel on the test socket has test loop and discharge return circuit, test loop with discharge return circuit is connected to on the test socket through the relay, the relay control the test socket respectively with test loop switch-on or with discharge return circuit switch-on.
2. 2. The KGD high temperature test system of claim 1 wherein the chip to be tested is flip-chip mounted to the test socket.
3. 3. The KGD high temperature test system according to claim 1, wherein the discharging circuit comprises a monitoring module and a switching module, the monitoring module is used for detecting a voltage parameter and a current parameter of the discharging circuit, and the switching module is used for opening and closing according to the value of the voltage parameter or the current parameter so as to protect a chip.
4. 4. The KGD high-temperature testing system according to claim 3, wherein the monitor module comprises a DW01 chip for turning off the discharge loop when the voltage in the discharge loop exceeds a highest voltage threshold or is lower than a lowest voltage threshold, and the DW01 chip turns off the discharge loop when the current in the discharge loop exceeds a highest current threshold.
5. 5. The KGD high temperature test system according to claim 4 wherein the switch module comprises an AO4407 chip for controlling the AO4407 chip to open a discharge loop to achieve a normal discharge when the voltage in the discharge loop is between a highest voltage threshold and a lowest voltage threshold and when the current in the discharge loop is below a highest current threshold.
6. 6. The KGD high temperature test system according to claim 5 wherein pin 1 of the DW01 chip is connected to pin 4 of the AO4407 chip through one AO3401 chip, pin 2 of the DW01 chip is connected to pins 1, 2 and 3 of the AO4407 chip through another AO3401 chip, and pin 2 of the DW01 chip is connected to a relay through a resistor R10, pin 5 of the DW01 chip is connected to Vin, and pins 5, 6, 7 and 8 of the AO4407 chip are all connected to Vout.
7. 7. The KGD high temperature test system of claim 6 wherein pin 1, pin 2, and pin 3 of the AO4407 chip are connected to Vin.

Description

KGD high temperature test system Technical Field The application belongs to the field of semiconductor testing, and particularly relates to a high-temperature testing system suitable for SiC_KGD. Background KGD (Known Good Die) testing refers to functional and performance testing of die (die) prior to chip packaging to ensure its yield prior to packaging. With the continuous progress of semiconductor technology, particularly the wide application of third generation semiconductor materials (such as SiC, gaN), the importance of KGD testing is becoming increasingly prominent. However, most of the existing KGD test schemes continue to use the finished test method of the conventional silicon-based (Si-based) chip, which exposes some problems when testing the new material chip. First, in dynamic testing, the system fails to reserve a self-discharge loop for the chip when switching test loops. This can result in the charge accumulated by the chip during the test not being effectively released, thereby affecting the accuracy of the test results and possibly even damaging the chip. Particularly, under the application scenes of high voltage and high frequency, the problem of charge accumulation is more serious, and the problem of self-oscillation gate oxide breakdown of the chip is easy to cause; Secondly, when short circuit is tested, the protection response time of the existing test system is insufficient. The third-generation semiconductor material has higher switching speed and lower on-resistance, so that the rising speed of short-circuit current is extremely high, and the response time of a protection mechanism of the traditional test system is long, so that the current cannot be cut off in time, and the chip and the test socket are damaged due to overcurrent in the test process. This problem is particularly pronounced in high power density applications, severely affecting test reliability and chip yield. Therefore, there is a need for a KGD high temperature test system for third generation semiconductors. Disclosure of utility model In order to solve the defects in the prior art, the application provides a KGD high-temperature test system and a test method, which solve the problems of KGD test of a high-current chip, low yield, burnout of a test SOCKET (SOCKET) and the like when the chip is subjected to high-temperature test (such as 150 DEG and 175 DEG) and the like under the high-temperature condition. The technical effects to be achieved by the application are realized by the following scheme: According to a first aspect of the present application, there is provided a KGD high temperature test system, comprising a test socket, a test loop and a discharge loop are connected in parallel to the test socket, the test loop and the discharge loop are connected to the test socket through a relay, and the relay controls the test socket to be respectively connected with the test loop or the discharge loop. Preferably, the chip to be tested is mounted on the test socket in a flip-flop manner. Preferably, the discharging loop comprises a monitoring module and a switch module, wherein the monitoring module is used for detecting the voltage parameter and the current parameter of the discharging loop, and the switch module is used for opening and closing according to the numerical value of the voltage parameter or the current parameter so as to protect the chip. Preferably, the monitoring module comprises a DW01 chip, wherein the DW01 chip is used for switching off a discharge loop when the voltage in the discharge loop exceeds a highest voltage threshold or is lower than a lowest voltage threshold, and switching off the discharge loop when the current in the discharge loop exceeds a highest current threshold. Preferably, the switching module comprises an AO4407 chip, and the AO4407 chip is used for controlling the AO4407 chip to open a discharge loop to realize normal discharge when the voltage in the discharge loop is between a highest voltage threshold and a lowest voltage threshold and when the current in the discharge loop is lower than a highest current threshold. Preferably, pin 1 of the DW01 chip is connected to pin 4 of the AO4407 chip through one AO3401 chip, pin 2 of the DW01 chip is connected to pins 1, 2 and 3 of the AO4407 chip through the other AO3401 chip, and pin 2 of the DW01 chip is connected to the relay through a resistor R10, pin 5 of the DW01 chip is connected to Vin, and pins 5, 6, 7 and 8 of the AO4407 chip are all connected to Vout. Preferably, pin 1, pin 2, and pin 3 of the AO4407 chip are connected to Vin. According to the embodiment of the application, the KGD high-temperature test system has the beneficial effects that the short-circuit current can be completely limited by adding the discharge loop and performing the current limiting setting, so that the test socket is better protected, the problems that the conventional test loop has larger noise, the test loop is not subjected to current l