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CN-224232175-U - Functional detection and verification platform for RISC-V architecture

CN224232175UCN 224232175 UCN224232175 UCN 224232175UCN-224232175-U

Abstract

The utility model provides a functional detection and verification platform for RISC-V architecture. The device comprises a RISC-V processor, wherein an HPC_A connector and an HPC_B connector are arranged on the RISC-V processor, the HPC_A connector is connected with a FLASH memory and an SRAM memory, and the HPC_B connector is connected with a CAN bus, a QSPI interface, a NAND memory, a SPACE WIRE bus, an IIC bus, a UART transmitter, PWM, a 1553B bus and an SPI interface. The utility model relates to the technical field of integrated circuit design verification platforms.

Inventors

  • ZHANG JUNWEI
  • YE ZHENRONG
  • ZHAO LI

Assignees

  • 珠海航宇微科技股份有限公司

Dates

Publication Date
20260512
Application Date
20250519

Claims (4)

  1. 1. The functional detection and verification platform for the RISC-V architecture comprises a RISC-V processor, and is characterized in that an HPC_A connector (1) and an HPC_B connector (2) are arranged on the RISC-V processor, the HPC_A connector (1) is connected with a FLASH memory (3) and an SRAM memory (4), and the HPC_B connector (2) is connected with a CAN bus (5), a QSPI interface (6), a NAND memory (7), a SPACE WIRE bus (8), an IIC bus (9), a UART transmitter (10), a PWM, a 1553B bus (11) and an SPI interface (12).
  2. 2. A functional test and verification platform for RISC-V architecture according to claim 1, wherein said FLASH memory (3) comprises an 8-bit FLASH memory (13), a 16-bit FLASH memory (14) and a 32-bit FLASH memory (15), and said SRAM memory (4) comprises an 8-bit SRAM memory (16), a 16-bit SRAM memory (17) and a 32-bit SRAM memory (18).
  3. 3. A functional test and verification platform for RISC-V architecture according to claim 2, wherein the 8-bit FLASH memory (13) has a chip model of SST39LF, the 16-bit FLASH memory (14) has a chip model of S29GL01GS, the 32-bit FLASH memory (15) has a chip model of SST39VF6401, and the 8-bit SRAM memory (16), the 16-bit SRAM memory (17) and the 32-bit SRAM memory (18) each have a chip model of IS61WV20488ALL.
  4. 4. A functional test and verification platform for RISC-V architecture as claimed in claim 1, wherein said NAND memory (7) comprises an 8-bit NAND memory (19) and a 16-bit NAND memory (20).

Description

Functional detection and verification platform for RISC-V architecture Technical Field The utility model relates to the technical field of integrated circuit design verification platforms, in particular to a functional detection verification platform for RISC-V architecture. Background RISC-V is an open instruction set architecture that allows anyone to use, modify and implement. This openness has prompted a variety of innovations, particularly flexible designs in academic research and commercial applications. The RISC-V design is compact compared to the traditional proprietary architecture, which makes it relatively easy to implement, suitable for education and experimentation. Hardware verification is an important element in ensuring design correctness, particularly in integrated circuit designs, where the complexity of verification is proportional to the design complexity. For RISC-V architecture, the hardware verification platform needs to meet the requirements of ensuring that all instructions and functions work as intended, including basic operations, memory access, interrupt handling, etc., verifying performance of the design under different workloads, including metrics such as timing, power consumption, throughput, etc., and compatibility verification, ensuring compatibility of the new design with existing RISC-V ecosystems, including different extensions and variants. The verification platform needs to detect potential security vulnerabilities to ensure that the design is protected from attack. With the continued expansion of RISC-V architecture, the complexity of the design increases. This includes multi-core processors, accelerators, different peripheral interfaces, etc. In order to ensure the correctness and performance of the design, it is important to develop an efficient hardware verification platform. The prior art of RISC-V interface hardware verification platforms has some drawbacks, mainly including the lack of standardization of the interface, although the RISC-V instruction set itself is open, the low degree of standardization with other peripherals and interfaces may lead to compatibility problems between different implementations, and in RISC-V systems, the integration testing of the interface may face challenges, especially in multi-core or complex systems, where additional work is required to verify interactivity and stability between different modules. These drawbacks may affect the efficiency and effectiveness of the RISC-V interface hardware validation platform. Disclosure of utility model Aiming at the problems existing in the prior art, the utility model provides a functional detection and verification platform for RISC-V architecture. The aim is to verify the compatibility of RISC-V processors with various peripherals. In order to achieve the purpose, the technical scheme adopted by the utility model is that the functional detection and verification platform for the RISC-V framework comprises a RISC-V processor, wherein an HPC_A connector and an HPC_B connector are arranged on the RISC-V processor, the HPC_A connector is connected with a FLASH memory and an SRAM memory, and the HPC_B connector is connected with a CAN bus, a QSPI interface, a NAND memory, a SPACE WIRE bus, an IIC bus, a UART transmitter, a PWM (pulse width modulation), a 1553B bus and an SPI interface. Further, the FLASH memory (3) comprises an 8-bit FLASH memory, a 16-bit FLASH memory and a 32-bit FLASH memory, and the SRAM memory comprises an 8-bit SRAM memory, a 16-bit SRAM memory and a 32-bit SRAM memory. Further, the chip model of the 8-bit FLASH memory IS SST39LF, the chip model of the 16-bit FLASH memory IS S29GL01GS, the chip model of the 32-bit FLASH memory IS SST39VF6401, and the chip models of the 8-bit SRAM memory, the 16-bit SRAM memory and the 32-bit SRAM memory are IS61WV20488ALL. Further, the NAND memory comprises an 8-bit NAND memory and a 16-bit NAND memory. In summary, the utility model can realize functional verification, performance test, compatibility check and system integration test of RISC-V architecture. The function verification can ensure that the processor can correctly communicate with the peripheral, execute instructions and process data, and verify whether the hardware design accords with the expected function, and the performance test is mainly used for evaluating the influence of different peripheral on the system performance, including the data transmission rate, the response time and the processing speed, so as to optimize the system design. The compatibility check mainly verifies the compatibility of the RISC-V architecture with various peripherals, ensuring that they can cooperate seamlessly, especially in terms of different data formats and protocols. The utility model can effectively promote the research and the development and the application of the RISC-V related technology and improve the reliability and the efficiency of the system. In order to more clearly illustrate