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CN-224232176-U - Bridge chip die, memory device and electronic system

CN224232176UCN 224232176 UCN224232176 UCN 224232176UCN-224232176-U

Abstract

A bridge chip die, a memory device, and an electronic system are provided. The bridge chip die is used for being connected with at least one DRAM chip die, wherein the bridge chip die is used for being integrated with the at least one DRAM chip die through 3D packaging, the bridge chip die comprises one or more UCIe interfaces, a plurality of DRAM controllers, a Cache controller and an SRAM, each of the plurality of DRAM controllers is used for accessing a corresponding DRAM block, each of the plurality of DRAM controllers comprises a 3D DRAM interface, when the main plane of the bridge chip die is attached to the main plane of a first DRAM chip die in the at least one DRAM chip die, the 3D DRAM interface of each DRAM controller is correspondingly connected with the DRAM interface of each DRAM block of the first DRAM chip die, and the Cache controller is used as the Cache of the at least one DRAM chip die.

Inventors

  • XU XIAOHUA

Assignees

  • 上海赋昇科技有限公司

Dates

Publication Date
20260512
Application Date
20250611

Claims (10)

  1. 1. Wherein each of the at least one DRAM chip die comprises a plurality of DRAM blocks, the bridge chip die being for integration with the at least one DRAM chip die by 3D packaging; The bridging chip grain comprises one or more UCIe interfaces, a plurality of DRAM controllers, a Cache controller and SRAM; Each of the plurality of DRAM controllers is for accessing a corresponding DRAM block, the respective corresponding DRAM blocks of different DRAM controllers being different from each other; When the main plane of the bridge chip die is attached to the main plane of a first DRAM chip die of the at least one DRAM chip die, the 3D DRAM interface of each DRAM controller is correspondingly connected with the DRAM interface of each DRAM block of the first DRAM chip die; The Cache controller and the SRAM are used as a Cache of the at least one DRAM chip grain, and the SRAM is used as a Cache line of the Cache controller.
  2. 2. The bridge chip die of claim 1, further comprising a first bus; each of the one or more UCIe interfaces is connected with the Cache controller; the Cache controller is connected with the plurality of DRAM controllers through the first bus; Each of the one or more UCIe interfaces provides the received storage space access request to the Cache controller; the Cache controller accesses any one of the plurality of DRAM controllers through the first bus.
  3. 3. The bridge chip die of claim 1, comprising a first bus, a plurality of UCIe interfaces, and a plurality of Cache controllers; each of the plurality of Cache controllers is connected with one of the plurality of UCIe interfaces; The plurality of Cache controllers each have a Cache line; the memory spaces accessible by the plurality UCIe of interfaces at least partially overlap one another; Each Cache controller and the Cache line thereof are used as the Cache of the memory space which can be accessed by the UCIe interface connected with the Cache controller; The plurality of Cache controllers are all connected with the plurality of DRAM controllers through the first bus; The bridging chip grain also comprises a circuit for processing consistency, and the circuit for processing consistency maintains consistency among caches of the plurality UCIe of interfaces.
  4. 4. The bridge chip die of claim 1, further comprising a second bus, and a plurality of Cache controllers; the one or more UCIe interfaces are connected to the second bus; the Cache controllers are connected with the second bus; the Cache controllers are in one-to-one correspondence with the DRAM controllers.
  5. 5. The bridge chip die of any one of claims 1-4, comprising a first UCIe interface and a second UCIe interface; The memory space accessible by the memory space access requests received from each of the first UCIe interface and the second UCIe interface are identical to, different from, or partially overlap with each other.
  6. 6. The bridge chip die of claim 5, comprising a plurality UCIe of interfaces; each of the plurality UCIe of interfaces is used to connect a logic chip or other bridge chip die.
  7. 7. The bridged-chip die of claim 1, wherein the bridge chip die comprises a plurality of die, The 3D DRAM interface is positioned in the edge area of the main plane of the bridging chip die; The one or more UCIe interfaces are located at an edge region of the main plane of the bridge chip die that is not occupied by the 3D DRAM interface; The Cache controller and the SRAM are located in an area of the main plane of the bridge chip die that is not occupied by the 3D DRAM interface and the one or more UCIe interfaces.
  8. 8. The bridged-chip die of claim 4, wherein the bridge chip die further comprises a plurality of die pads, The 3D DRAM interface is positioned in the edge area of the main plane of the bridging chip die; The one or more UCIe interfaces are located at an edge region of the main plane of the bridge chip die that is not occupied by the 3D DRAM interface; The second bus is positioned in the central area of the main plane of the bridging chip crystal grain; The Cache controller and the SRAM are located between the area occupied by the second bus and the area occupied by the 3D DRAM interface of the main plane of the bridge chip die.
  9. 9. A memory device comprising a bridge die and at least one DRAM die; The bridge chip die and the at least one DRAM chip die are integrated together by a 3D package; The bridge chip die is a bridge chip die according to claim 4.
  10. 10. An electronic system comprising a first storage device and a second storage device; the first storage device and the second storage device are each the storage device according to claim 9; The first memory device and the second memory device are connected with UCIe port of the bridge chip die of the second memory device through UCIe port of the bridge chip die of the first memory device.

Description

Bridge chip die, memory device and electronic system Technical Field The present application relates to the field of integrated circuit chips, and in particular to 3D-DRAM based external storage schemes. Background Generally, when a chip requires high-performance, high-capacity external storage, a DDR controller is used to connect the memory chip. The DDR controller interacts with the memory chip following the DDR protocol. The current DDR protocol has been promulgated to DDR5, with frequencies up to 6400MHz and even higher. Take DDR5 DIMMs as an example, a 32-bit dual channel specification. The corresponding total bandwidth is 32bx6.4g x2=4x 6.4x2= 51.2GB per second. To support higher bandwidths, the latest GDDR technique may be selected so that higher frequencies and bandwidths may be achieved. One high performance SOC chip often integrates one or more DDR controllers to meet higher bandwidth demands. Fig. 1 shows a case where one logic chip contains 8 dual channel DDR5 controllers. Since DDR memory also typically has a chip form. The "logic chip" is used herein to distinguish it from the DDR memory chip. The logic chip of fig. 1 includes 8 DDR controllers (bit controller 1-controller 8 shown). Each DDR controller is respectively connected with the corresponding DDR4 memory chip. By increasing the number of DDR controllers in the logic chip, the memory capacity and bandwidth available to the logic chip can be increased. However, in the logic chip of the conventional 2D structure, the number of DDR controllers is limited by the area of the logic chip and the number of pins. Further, the manner of wiring the DDR controller to the DRAM chip is limited such that the DDR controller can only be wired from the side of the logic chip, which limits the number of pins that the logic chip can provide for use by the DDR controller. Increasing the area and the number of pins of the logic chip will seriously increase the cost of the logic chip, thereby resulting in a decrease in the market competitiveness of the logic chip. The 3D-DRAM is a form of a memory product proposed to solve the above-mentioned problems, in which dies of two or more chips are bonded in a direction perpendicular to a principal plane of the dies by a 3D packaging technique to form a chip including both logic chip dies and DRAM chip dies. Allowing the logic chip die and the DRAM chip die to be connected from a higher dimension. And the two grains are very short in distance, and PHY (physical layer interface circuit) or IO (input/output) circuits with strong driving capability are not needed to be connected between the grains, so that the implementation cost is reduced. Even if the core voltage needs to be converted, only the voltage conversion circuit needs to be optionally added. FIG. 2A is a schematic diagram of a DRAM chip die and logic chip die combination. By way of example, a number of 256-bit, 400MHz interfaces are reserved on the DRAM chip die, one for each DRAM block in FIG. 2A. The die of the DRAM chip and the die of the logic chip are directly bonded by surface contact (e.g., connected by TSVs). Because the two are in surface contact, the number of pins capable of being connected is far greater than that in the traditional 2D structure connection mode. For example, on an area of 100mm 2, 64 such interfaces (256 bits per interface) are implemented, so that a bandwidth of 256b x 400Mhz x 64 =32bx0.4gx64=12.8x64 gbps= 819.2 GBps can be implemented. Equivalent to 16 bandwidths that can be provided by the 32b x 6.4G x 2 DDR5 controllers mentioned earlier. Fig. 2B shows a schematic diagram of the principal plane of the logic chip die. Each light square in fig. 2B represents an area corresponding to 1 DRAM block after bonding. Each light square also includes an interface location represented by a dark square for interfacing with 256 bits of a corresponding DRAM block. It will be appreciated that the light squares of fig. 2B do not necessarily represent that the circuit layout within the logic chip needs to be divided by square areas, but the interface locations represented by the dark squares are provided with pins of interface circuits for communicating with the DRAM blocks, so that the wiring of the circuits within the logic chip is affected by the interface circuits. In the 3D DRAM scheme illustrated in fig. 2A and 2B, the form of the 3D packaged DRAM greatly limits the design flexibility of the logic chip: 1. the logic chip die needs to occupy a large area (dark area of fig. 2B) for connecting low-speed 3D-DRAM interfaces, which results in a not high memory bandwidth density ratio; 2. Meanwhile, the position of the interface is fixed, and the layout and the wiring of the logic chip crystal grains are limited, so that the area utilization rate of the logic chip crystal grains is reduced, and the wiring mode of the logic chip crystal grains is limited; 3. The need to package the logic chip with the DRAM chip die using 3D packaging techniques