CN-224232179-U - YAO32 development mainboard

Abstract

The utility model relates to the field of embedded electronic circuits, discloses a YAO32 development main board, and aims to solve the defects of the existing development board in compatibility, electrical characteristics and cost control. The development main board comprises a main control module, a clock module, a debugging downloading module, an external interface module, a key module, an indicator light module, a power management module and a USB module, wherein the main control module adopts a YAO32F107Q100 chip, and each functional module is compact in design, reasonable in matching, and has the advantages of perfect interface signal extraction, flexible debugging mode, stable power supply system and the like. The development main board enhances the adaptability and debugging support capability of the YAO32F107Q100 chip by optimizing the USB circuit, the power supply voltage stabilization, the clock source configuration and the external pin layout, obviously reduces the complexity and the manufacturing cost of the whole system on the premise of ensuring practical functions, and is suitable for the development and evaluation scenes of the chip.

Inventors

• YANG KAIQI

Assignees

• 武汉鲧禹智能科技有限公司

Dates

Publication Date

20260512

Application Date

20250711

Claims (3)

1. 1. The YAO32 development main board comprises a main control module, a clock module, a debugging downloading module, an external interface module, a key module, an indicator light module, a power management module and a USB module, wherein the clock module, the debugging downloading module, the external interface module, the key module, the indicator light module, the power management module and the USB module are connected with the main control module, the USB module comprises a Type-C interface (USB 1) circuit, a Micro-USB interface (USB 2) circuit and a CH340N USB-to-serial circuit, a DP signal line of the Type-C interface (USB 1) circuit is connected with a USB_DP pin of the main control module through a resistor R24, a DM signal line is connected with a USB_DM pin of the main control module through a resistor R25, the DP signal line is connected with a 3.3V power supply through a pull-up resistor, a VBUS pin is grounded through a decoupling capacitor, and the Micro-USB interface (USB 2) circuit comprises a power switch SW1 and a fuse F1, and the external interface module is composed of three multi-pin connectors, wherein the memory interface (MC), the analog-to-digital conversion (ADC), serial communication (USART, SPI, I C), a Timer (TIM) and the debugging interface and the USB pin are debugged.
2. 2. The YAO32 development motherboard of claim 1, wherein the master module uses a chip model YAO32F107Q100, and a plurality of GPIO pins PA0 to PA15, PB0 to PB15, and PC0 to PC15 are connected to other modules.
3. 3. The YAO32 development board of claim 1, wherein the voltage regulator circuit chip in the power management module is YAO1117ST-3.3, the input terminal VIN is connected to ground via a capacitor, and the output terminal TAB is connected to ground via a capacitor.

Description

YAO32 development mainboard Technical Field The utility model relates to the field of embedded electronic circuits, in particular to a YAO32 development main board. Background The microcontroller development board is used as a hardware experiment platform for embedded system development, the universality design of the microcontroller development board is difficult to meet the optimization requirement of a specific chip, the existing development board is difficult to meet the problems of debugging compatibility, interface electrical characteristics, power supply time sequence and the like of the YAO32F107Q100 chip, and meanwhile, the existing development board is redundant in function and high in cost. Disclosure of utility model In order to solve the problems, the utility model aims to provide a low-cost YAO32 development main board which is adaptive to a YAO32F107Q100 chip, and has good universality and debugging adaptability. The technical scheme adopted by the utility model is as follows: The YAO32 development main board comprises a main control module, a clock module, a debugging downloading module, an external interface module, a key module, an indicator light module, a power management module and a USB module, wherein the clock module, the debugging downloading module, the external interface module, the key module, the indicator light module, the power management module and the USB module are connected with the main control module, the power management module and the USB module are tightly matched in design, the functions are clear, the structure is reasonable, and the complexity and the cost of a system are remarkably reduced. Further, the core of the main control module is a YAO32F107Q100 chip (U1). The Micro-USB circuit (USB 2) of the USB module is connected with the USB OTG FS pin of the MCU, the USB_DP and USB_DM signals of the MCU are respectively connected with the D+ and D-pins of the Micro-USB circuit through a 22Ω series resistor, a 1.5kΩ pull-up resistor is connected to 3.3V on the USB_DP line, the ID pin of the Micro-USB circuit is connected to the USB_ID input of the MCU, and the VBUS pin of the Micro-USB is connected to the power management module. Further, in the voltage stabilizing circuit of the power management module, the input end and the output end of YAO1117ST-3.3 are respectively provided with a 10 mu F electrolytic capacitor and a 0.1 mu F decoupling capacitor, the input end is connected with a +5V power supply, and the output end outputs 3.3V. Further, the external interface module is composed of three multi-pin connectors, which lead out of the memory interface (FSMC), analog-to-digital conversion (ADC), serial communication (USART, SPI, I C), timer (TIM), debug interface (JTAG) and function pins of USB of the MCU of the main control module. Further, the two ends of the main clock crystal oscillator X2 (8 MHz) of the clock module are respectively connected to the OSC_IN and OSC_OUT pins of the MCU through a 20pF load capacitor, a 1MΩ resistor is connected IN parallel inside, and the low-speed clock crystal oscillator X1 (32.768 kHz) is connected to the OSC32_IN and OSC32_OUT pins of the MCU through two 10pF load capacitors. Further, the debugging downloading module comprises a USB-to-serial circuit and a hardware debugging interface, USB D+ and D-pins of a CH340N circuit are connected with a Type-C interface seat through 22 omega resistors and pulled down to GND through 5.1k omega resistors, 3.3V voltage stabilization is integrated in the CH340N, 0.1 mu F capacitance decoupling is additionally arranged on a V3 pin of the USB-to-serial circuit, UART interface pins TXD and RXD of the CH340N are connected with a USART pin of an MCU through configurable jumpers, a middle pin of a Boot mode selection jumper circuit H4 is connected with BOOT0 and BOOT1 of the MCU respectively, one side of the pins is connected with a 3.3V power supply and the other side is connected with the ground, and the BOOT pin is in a shortage and pulled down to ground BOOT0 or pulled up/pulled down to a fixed level through 10k omega resistors respectively Further, one end of KEY3 of the KEY module is connected to NRST pins of the MCU, the other end is grounded, one end of KEY1 and KEY2 of the user is connected to a universal input pin of the MCU, the other end is grounded, and a pull-up resistor is arranged at the pin end of the MCU. Further, the anode of the indicator lamp module LED2 is connected to a +3.3V power supply through a current limiting resistor, the cathode is grounded, and the LED0 and the LED1 are respectively connected between two GPIO pins of the MCU and the power supply/ground through the current limiting resistor. Drawings FIG. 1 is a schematic circuit diagram of a master control module of the present utility model; FIG. 2 is a schematic diagram of a clock module circuit of the present utility model; FIG. 3 is a schematic circuit diagram of a debug download module of the present utility mo